Is there a multiplexer with latched output?

[whack]

Hey all,

I need a multiplexer for my project that will hold output until a next control pin event when it will latch a new value. Basically a multiplexer with a built-in latch or flip-flop.

So the pins should be input 1, input 2, output, select, latch/gate/clock. For example the latch control can be connected to a clock signal to hold a new value on clock edge.

I understand that I can add a latch or flip-flop after a multiplexer but I was wondering if there's a one chip solution for this.

Could someone show me an example of an off-the-shelf part and recommend one for my project? I need two multiplex two 12-bit (or 16-bit) data inputs.

 

[FvM]

Semiconductor manufacturers, e.g. TI, have search machines for their logic ICs. It's the straightforward way to find out which logic functions are available.

Could someone show me an example of an off-the-shelf part and recommend one for my project? I need to multiplex two 12-bit (or 16-bit) data inputs.

Sounds like you need 1 latch/FF and 12 or 16 2:1 mux functions. Having the latch or not doesn't matter much in this case.

 

[whack]

Semiconductor manufacturers, e.g. TI, have search machines for their logic ICs. It's the straightforward way to find out which logic functions are available.


Sounds like you need 1 latch/FF and 12 or 16 2:1 mux functions. Having the latch or not doesn't matter much in this case.

I'm actually not sure what you mean.

In my case the inputs of the multiplexer can change between valid, undefined and hi-Z states, I need the multiplexer output to hold a value regardless of input value change until the clock or control pin is asserted to accept the new value. Normal multiplexer only has a select pin.

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If I made a truth table for this component, would it help to explain what I need?

 

[FvM]

My fault, I understood latching the select signal.

I don't know any registered 2:1 muxes.

 

[apprenticemart2]

I don't really understand what you want but https://www.onsemi.com/PowerSolutions/product.do?id=MC10E167FNR2G

 

[whack]

My fault, I understood latching the select signal.

I don't know any registered 2:1 muxes.

I guess "registered" is the correct term. I'm trying to keep the component count down for a simpler PCB, even if these muxes will cost more. I'm new to PCB design so I just want as few chips as possible, with as few traces to route as possible.

I don't really understand what you want but https://www.onsemi.com/PowerSolutions/product.do?id=MC10E167FNR2G

That actually looks kind of like what I need. It says "1000MHz" minimum operating frequency... My circuit will be variable frequency switching between 14, 28 and 56MHz.
PLCC is kind of an odd package too for this application. I'd prefer SOIC or some type of SOP. No BGA please.

 

[FvM]

MC10xx is a PECL GHz logic series and surely not suitable for your application.

The next best fit in CMOS logic are "registered multiplexed bus exchangers" like SN74ALVCH162268.

 

[whack]

MC10xx is a PECL GHz logic series and surely not suitable for your application.

The next best fit in CMOS logic are "registered multiplexed bus exchangers" like SN74ALVCH162268.

I think I've used one of those (or similar) in a previous project. This one is bi-directional tri-state. While this is can work I don't really need bi-directional functionality. Still, if no other options this could be the one.

That's a good suggestion. Thanks!

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Oh wait, the one I used before is similar to this (also TI) but is just a plain tri-state transceiver, without the mux functionality. The one I used was 5V tolerant which was important because I was interfacing to 5V logic that time. I have yet to make measurements of the data input on the current project. Not sure what the voltage of the logic will be this time. I should probably get that done soon.

 

[whack]

Okay I borrowed an oscilloscope and made measurements on the bus I'm interfacing to, the logic pulses were 3.5-3.6V. I guess it should be safe to interface to 3.3V logic...?

I'm a little confused. I'm looking at TI catalog and I'm seeing multiple parts in "bus exchanger" category, but I'm not understanding the difference between parts that are just bus exchanger and registered bus exchanger. I noticed the parts without "registered" in the name also store the value on clock edge. So what's the difference?

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Take this one for example: SN74ALVCH16271
https://www.ti.com/lit/ds/symlink/sn74alvch16271.pdf

Transparent latches in the B-to-A path allow
asynchronous operation to maximize memory access
throughput. These latches transfer data when the
latch-enable (LE) inputs are low.

I'm not entirely sure about "Latch Enable" pin, does that make the device hold the original value of the input, even if the input value changes?

 

[KlausST]

Hi,

Latch enable:

The datasheet gives the answer:
See bottom truth table on page 2.

Klaus

 

[whack]

Hi,

Latch enable:

The datasheet gives the answer:
See bottom truth table on page 2.

Klaus

I saw the table. I didn't understand what it means besides that it indicates that the non-selected input is a "don't care".

Output level before the indicated steady-state input conditions were
established

What does this mean?

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And what happens to output on port A while output enable is low (active low) and latch enable goes from low to high (active low). Output enable is not in the same truth table as latch enable.

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Here's an improvised waveform:

Time ---->
/OEA LLLL
/SEL HHHH
-/LE LLHH
--1B 0101
---A 0???


Please fill in the ?-marks.

 

[FvM]

Besides possible data sheet confusions, I presume the difference between a clocked register (DFF) and a latch should be pretty clear. In so far I don't understand what the latest discussion is all about.

Not obvious by the designation, but the SN74ALVCH16271 bus exchangers include transparent latches before the mux (with active low latch enable) for the multiplexed B->A direction while the previously suggested registered bus exchangers have positive edge clocked registers. Decide what's suitable for your purposes.

 

[whack]

What's a transparent latch? Or rather, what makes a latch "transparent"?

And

Output level before the indicated steady-state input conditions were
established

What does this statement mean?

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I found this explanation:
https://people.csail.mit.edu/devadas/6.004/Lectures/lect4/sld010.htm

So when latch enable is high (active low) it keeps the old value regardless of input state change?

So back to the comparison of two bus exchanger parts, their difference is in how the output state is updated, one using low state, and the other signal edge (such as clock)...? So if I'm controlling these using an FPGA or CPLD, both parts can accomplish basically the same thing.

 

[FvM]

What's a transparent latch? Or rather, what makes a latch "transparent"?

Please allow me to quote the clear Wikipedia explanation:

Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-triggered). Although the term flip-flop has historically referred generically to both simple and clocked circuits, in modern usage it is common to reserve the term flip-flop exclusively for discussing clocked circuits; the simple ones are commonly called latches.

Using this terminology, a latch is level-sensitive, whereas a flip-flop is edge-sensitive. That is, when a latch is enabled it becomes transparent, while a flip flop's output only changes on a single type (positive going or negative going) of clock edge.

https://en.wikipedia.org/wiki/Flip-flop_(electronics)

 

[whack]

a latch is level-sensitive, whereas a flip-flop is edge-sensitive

So I can effectively accomplish the same thing with both parts if I control them using an FPGA or CPLD.

I'm thinking since I transmit video DAC data I have a steady zero output during video blanking, it would be better to use latched output rather than stopping the clock for clocked output. So I guess like it says in the title of the thread, I needed a latched multiplexer after all.

SN74ALVCH16271?

What do you think?

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Or maybe not... It seems like there's not a wrong way to do this between a latched or registered multiplexer.

 

[FvM]

I expect that both can be used. I would look at the timing diagram details to decide which is better suited. Also part availability can matter.

 

[KlausST]

Hi,

I'm thinking since I transmit video DAC data I have a steady zero output during video blanking,

Just to be sure:
Are you talking about the analog DAC output
Or the digital DAC input?

Our answers are only valid for digital ligic signals. No analog signals.

***
For "freezing" analog signals you need a "sample-and-hold" circuit.

Klaus

 

[whack]

Hi,



Just to be sure:
Are you talking about the analog DAC output
Or the digital DAC input?

Our answers are only valid for digital ligic signals. No analog signals.

***
For "freezing" analog signals you need a "sample-and-hold" circuit.

Klaus

Digital. 12bpp RGB data.

 

[KlausST]

Hi,

OK,

But doesn´t have the DAC a latch or a FF built inside?
I think usually they have...

Could you post a draft of your (expected) circuit?

Klaus

 

[whack]

Hi,

OK,

But doesn´t have the DAC a latch or a FF built inside?
I think usually they have...

Could you post a draft of your (expected) circuit?

Klaus

Well, the original plan is to use the existing resistor ladder DAC the machine contains, that has no latch or flip-flop, just resistors.

But it's an interesting suggestion, if I should choose to use a DAC chip instead. That's a backup plan.

Oh yeah. There will be drafts. I created one architecture schematic already, and then I thought of another candidate. I will be posting them. I will create another thread where I will show it and get comments, suggestions and criticism of the design. I will of course then revise it accordingly.

Thanks for the help!