Is there a dual-port SRAM to fit my need?

[whack]

I've got the following scenario:
First FSM on FPGA controls writing of continuous stream of digital pixel data, data goes into port 1 of some SRAM

Second FSM on FPGA controls reading of the data on port 2 of some SRAM, data read is double rate of input (with repetition)


Is there an SRAM that will fit the above scenario for continuous writing and continuous reading on two ports at the same time without interference? I suppose some sort of pipelining will be in play.

Can you suggest a part that fits this scenario?

Insight is appreciated.

 

[KlausST]

hi,

in detail it depends on datarate, data width, memory size...

If you only want to write at one port .. and only want to read at the other port .. then maybe a FIFO is mere suitable.

Dual port RAM:
Uusally they have no access problem as long as you don´t wirte to the same memory cell from both ports at the same time.

Klaus

 

[whack]

in detail it depends on datarate, data width, memory size...

The planned output datarate is up to 56MHz on output. (maybe 112MHz, but not mandatory)
Actual data width is 12 bits, closest common data width is 16 bit word, I guess.
For size I need 1M words.
So 1Mx16=16Mbit

If you only want to write at one port .. and only want to read at the other port .. then maybe a FIFO is mere suitable.

I need to traverse the data in a loop twice, so I don't see how I could use FIFO.
But otherwise true, one port always writes, one port always reads, but at different rates with separate address strobes.

Dual port RAM:
Uusally they have no access problem as long as you don´t wirte to the same memory cell from both ports at the same time.

Won't happen in my case.

To better visualize, I suppose you already understand that this is a video buffer. Now divide memory into two areas, upper area and lower area.
To one area the data is written, while to the other area the data is read from. Then their roles switch. In video terms we call this "page flipping".
So it goes like this:
Lower half is written to, upper half is read from (usually twice), then page flip, then upper half is written to while lower half is read from, then page flip and the cycle repeats.

My original design was to use two regular SRAMs to do the above but I then I found out dual-port memory exists, and sounds intriguing. I just don't know if it will work for my needs, it could potentially simplify the implementation.

- - - Updated - - -

I guess I should have also mentioned that I need it to have 3.3V I/Os and device package has to be non-BGA.

I found the closest dual-port SRAM I think I could use, but these aren't readily available. I'd have to order a whole tray, and there's only a couple single pieces available, and I'd have to pay like $250 for the single chip. Not happening.
The part is CYD18S18V18 and it doesn't even come in non-BGA package.

I checked out some FIFOs...
At least some FIFOs have mark and retransmit functionality, where I can mark the position of the read pointer and have it go back, but sadly that's not enough. I'd need to be able to mark at least two positions (beginning of scanline and beginning of frame), and reset read pointer separately from write pointer. Pretty neat feature on these FIFOs but doesn't get me all the way to what I need.

I guess short of someone suggesting a part for my scenario, I guess I'm back to square one with two regular SRAMs... :\

 

[FvM]

Synchronous SRAM can run with clock speeds of 200 or 250 MHz. Should be sufficient to implement the concurrent read/write access in FPGA logic through a single RAM port.

Another option would be using multiple slower asynchronous RAMs, trading data width against RAM speed.

 

[whack]

Synchronous SRAM can run with clock speeds of 200 or 250 MHz. Should be sufficient to implement the concurrent read/write access in FPGA logic through a single RAM port.

As often is the case with digital systems, there can be more than one valid solution. At this point the main challenge in my project is having too many choices of ways to implement.
Fast synchronous SRAM solves the problem of reading and writing pixel data at the same time, but creates a timing challenge for output as data reads are not at regular interval, which would force me to run it into a FIFO output buffer which will shift it out at a regular interval. That's either having an extra component or running the data through FPGA.

Dual-port would have been the simplest in terms of component count, pin count and simplicity of routing.

So synchronous SRAM is a valid solution but I don't see it being a clear winner.

Another option would be using multiple slower asynchronous RAMs, trading data width against RAM speed.

That's my original plan. On top of that I already have experience with those, so there's less risk of a severe mistake in the design.