Is the handling of TCP/IP stack faster when using a RTOS?

[cube007]

tcp ip vhdl

Hello,

The desired application needs to receive a data stream from a PC via Ethernet.

- minimum transfer rate is 1 MByte/s
- FPGA based design
- Processor: Soft-Processor Nios II from Altera
- Davicom DM9000 fast Ethernet controller (MAC/PHY)

At the moment I’m using a stand-alone TCP/IP stack (lwip from Microtronix) but the system is really slow (< 200 kByte/s). Of course there are ways to speed up the Ethernet driver, for example with DMA transfers. But what I would like to know is if a RTOS would result in a faster handling of the TCP/IP stack. Where are the advantages or disadvantages when using a RTOS like (uCos II, eCos, …)?


Thank you in advance,
niosIIuser

 

[brmadhukar]

dm9000 avr

Hi,
The rtos changing can give you a maximum of upto 350kbps only. You need to relook into your design and also some timing aspects of the HW.
brmadhukar

 

[cube007]

vhdl tcp ip

Hello brmadhukar,

Thank you for answering. Please tell me why I would get 350 kbps. I think that a RTOS would not speed up a design because of the overhead. Are there other advantages or disadvantages when using a RTOS?

Bye,
cube007

 

[7rots51]

tcp ip stack vhdl

I think if you use wiznet w3100 chip,your speed increases to above 1MB,

see the www.iinchip.com ,they provide tcpip stack in hardware ,they also provide IP core if you can buy.

The overead of CPU is very low in this case.
What is your idea?

 

[cube007]

w3100a stack source

Hello 7rots51,

The w3100 would be an alternative. But the chip costs more than the DM9000 from Davicom. The IP solution would burst the budget :? . There are some projects on implementing TCP/IP in VHDL/Verilog but these design are using a lot of logic elements of the FPGA and this is too expensive.
Yesterday I talked to a guy who is using lwip and DM9000 with an 8 Bit AVR uC from Atmel. The best performance he got was 255 kBytes/s. I think that the Nios should have enough power to speed up the transfer. First I try to improve the actual design (DMA, …). If this doesn’t help the Wiznet solution would be next.

Thanks for your contribution,
cube007

 

[Ace-X]

fpga dm9000

The PHY/MAC chip does not matter here, because DM9000 also supports 100Base interface, so the source for your problem lies in data exchange approach with DM9000 chip. You should know that it supports 8,16 or 32 bits transfer. Also, it has full-duplex flow control. I think you should check that your Nios<->DM9000 uses most of data bandwidth with pure Ethernet data (without TCP/IP). After that you will know which part of design is responsible for slow data rate.

 

[7rots51]

standalone application using uc-tcp/ip

Hi Cube007

The W3100A is not the same as DM9000 ,it is very different,read these and check site carefully:

W3100A is the world's first Ethernet based hardwired TCP/IP chip and contains all necessary Internet protocols (TCP, IP, UDP, ICMP, ARP, DLC and MAC) for Internet connectivity. Since W3100A's TCP/IP protocol stack is processed by hardwired logic, it provides high performance and ease the speed problem of Internet access was related to TCP/IP software and memory access. In addition, since OS is not mandatory, W3100A requires minimal sized ROM RAM, for MCU power and saves OS licensing fee.

- TCP, UDP, IP, ICMP, ARP, MAC hardwired logics included
- Support 4 independent channels simultaneously
- Up to 12Mbps data transmission speed
- MCU bus interface and I2C serial interface for MCU
- Standard MII interface for physical layer
- 16KBytes data buffer embedded
- 10/100 Base-T auto detection
- 3.3V internal operation, 5V tolerant I/Os

 

[cube007]

lwip nios

The PHY/MAC chip does not matter here, because DM9000 also supports 100Base interface, so the source for your problem lies in data exchange approach with DM9000 chip. You should know that it supports 8,16 or 32 bits transfer. Also, it has full-duplex flow control. I think you should check that your Nios<->DM9000 uses most of data bandwidth with pure Ethernet data (without TCP/IP). After that you will know which part of design is responsible for slow data rate.

Hello Ace-X,

In this design the DM9000 is connected via a 16 bit bus. Unfortunately there were not enough free IO pins for 32 bit :sm37: .
Testing the bandwidth between Nios and DM9000 is a good idea. I will make a PC application for sending a UDP data stream and capture only this data without using the TCP/IP stack. So the Nios Firmware will only get the data out of the DM9000 to test the bandwidth. If this bandwidth is too low a DMA module would speed it up – at least I think so.
The next step would be to run a profiler and check the lwip TCP/IP stack. It might be possible that for example checking the CRC of incoming/generating the CRC for outgoing packages needs a lot of time. A CRC is easily written in VHDL for doing this in hardware.

Thanks for your help.

The W3100A is not the same as DM9000 ,it is very different,read these and check site carefully

Hello 7rots51,

Sure the W3100 is totally different from normal Ethernet-Controllers like the DM9000. But the Wiznet solution is dearer and needs more space because the design would need an extra PHY. I try to find the solution with the DM9000/lwip. In the case that the bandwidth is still too slow the Wiznet would be the next alternative.

Regards,
cube007