syedshan
Advanced Member level 1
- Joined
- Feb 27, 2012
- Messages
- 463
- Helped
- 27
- Reputation
- 54
- Reaction score
- 26
- Trophy points
- 1,308
- Location
- Jeonju, South Korea
- Activity points
- 5,134
downsampling 40 MHz to 5 MHz in vhdl
hello every one,
I have a high speed adc which I am giving the clock of 40 MHz. Now my requirement is such I need only the signals equivalent to 5 Mhz clock-related signal hence I am doing so by following method.
Is this alright. I read about down-sampling that for high frequency components we might have aliasing issues, (but I am thinking that taking only every 8th data wont hurt the signals much...!!?? note sure though
PS. Note that the clock frequency even for the down-sampled sample is 40 MHz but since the data is stored in FIFO first, hence I am enabling wr_en at respective intervals.
hello every one,
I have a high speed adc which I am giving the clock of 40 MHz. Now my requirement is such I need only the signals equivalent to 5 Mhz clock-related signal hence I am doing so by following method.
Is this alright. I read about down-sampling that for high frequency components we might have aliasing issues, (but I am thinking that taking only every 8th data wont hurt the signals much...!!?? note sure though
Code:
process(clkHIGHM, rst)
begin
if(rst = '1') then
cntr <= 0;
fwr_en <= '0';
wr_cnt <= 0;
wr_stop <= '0';
elsif(rising_edge(clkHIGHM)) then
if(f_full = '0' and wr_stop = '0') then
if(cntr < div_factor-1) then //div_factor = 8
cntr <= cntr + 1;
fwr_en <= '0';
else
cntr <= 0;
fwr_en <= '1';
wr_cnt <= wr_cnt + 1;
end if;
elsif(f_full = '1') then
wr_stop <= '1';
fwr_en <= '0';
end if;
end if;PS. Note that the clock frequency even for the down-sampled sample is 40 MHz but since the data is stored in FIFO first, hence I am enabling wr_en at respective intervals.