vivek
Member level 4
verilog future
Hi
System verilog is now statndardized and has loads of industry support. Since it is a HDVL will SV proceeed to replace standard verilog/VHDL in design? Will SV slowly replace Vera and Specman/E as the language for verification? Please share your views on this..
Thanks
Vivek
Hi
System verilog is now statndardized and has loads of industry support. Since it is a HDVL will SV proceeed to replace standard verilog/VHDL in design? Will SV slowly replace Vera and Specman/E as the language for verification? Please share your views on this..
Thanks
Vivek