Is synchronous or asynchronous design prefered?

[pratibha m d]

Sync or async design?

Is synchronous or asynchronous design prefered?
Plz give reasons. Async design is usually infered by a Latch in FPGA design while sync design by a flop.
So, which is the better idea of designing?

 

[khamitkar.ravikant]

Sync or async design?

is always better to have sync. design as flip flop output at given time are predictable and the events occure at clock events so it is always better to use sync. design.
if u go for async. design then the performance of FPGA get hamperd and u will not get best results.
if u want to check the same even xilinx gives same warning when u use language templates.
u can go to xilinx ISE's Edit -> language template -> VHDL -> synthesis construct -> coding example -> and then u can check any of the examples which is sync. or async.
xilinx will give warning about async. designs.
check that.

 

[pratibha m d]

Re: Sync or async design?

Firstly I would like to thank you for the reply.
I tried an async D flip flop in ISE. But i didn't get any warnings. I am using ISE 9.1
Can you plz suggest how can I learn Timing analysis in Front end design? I mean any evaluation version tools ?

 

[radix]

Re: Sync or async design?

pratibha m d,

What is an async flip-flop in vhdl/verilog?

A flip-flop is what actually makes a design synchronous since it is a clocked element. Other digital circuits such as and, or, xor, and muxes are async devices but flops and counters change on clock edges and capture the state of the other async devices.

You might want to pick up a book on digital design to get familar with some of the concepts. Truly async design is supposed to be an even lower power alternative to sync design since you don't have free running clocks.

Most designs in FPGAs/ASICs are sync designs. Or at least they try to be!

Radix