Is 'Reuse Methodology Manual' suitable for PLD designer?

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ifarmer

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I found the book, Reuse Methodology Manual for System-on-a-Chip Designs third edition, is writed for ASIC designer.
So is it suitable for PLD designer?
Thanks.
 

I think you r on your way. it's a good refference for professional designs.
 

it is very helpful for cpld/fpga designer if you follow the rule.
I hope I read it several years ago. my old vhdl code is only reusable for me
 

Reuse Methodology Manual is no more than coding guidelines on which tons of material is already available free.

Delay (delayed by technology)
 

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