Is 'Reuse Methodology Manual' suitable for PLD designer?

[ifarmer]

I found the book, Reuse Methodology Manual for System-on-a-Chip Designs third edition, is writed for ASIC designer.
So is it suitable for PLD designer?
Thanks.

 

[ydao]

I think you r on your way. it's a good refference for professional designs.

 

[speedoak]

it is very helpful for cpld/fpga designer if you follow the rule.
I hope I read it several years ago. my old vhdl code is only reusable for me

 

[delay]

Reuse Methodology Manual is no more than coding guidelines on which tons of material is already available free.

Delay (delayed by technology)