Is it REALISTIC to use FPGAs for portable applications?

I want to have a better idea of the power requirments for most of the mid range FPGA ( spartan 3 and others like) i discovered this documents : comming from Ti **broken link removed** .

Now has any body used FPGAs for portable solutions here?.. how can i manage the power to keep it as low as possible .. I know from all times that the power consumption on a FPGA is proportional to the number of gates switching at the same time .. Basically can a portable SoC type of solution can be implemented on any type of FPGA or are ther some to avoid ..
i look at the VIRTEX II pro .. this chips as small as they, are can take as much as 10 Amps at 1.5 V !!!!!!!!!!!
So out the question to put them on a satellite !
so any documents that you can advice??

There are many types of FPGA technics. For the common used one-- SRMA-based FPGA, you can't use it for the portable device because it costs too much power. When the system is shut down, to retain the content in FPGA ,u should equips the device with a powful backup batter. limited by the bulk about portable device, it is so difficult.

thanks eltonjohn... TI maerial is very informative...
I think power requirements is more related to no. of devices conncted to FPGAs.. so if u will go thru SRAM based tech.. then obviously power cons. will be more and its not very suitable for satellite application. i think spartan-3 is a good solution....

Well is not that simple i found a great paper by Xilinx in the Xcell journal Fall 2002 .They adress those isues and a lot need to be considered .Specially coding style by doing design constrains and recomend to shut down logic when not in use .Well if the constrains are : TO MEET product deadlines This is a BIG CONCERN because you have one more BIG PROBLEM and is time .. Xilinx basically advices to use AMLIFY Physical Synthesis to help you to meet your power requiremets ..
But just for the RECORD let me mention what need to be dealt with :

*Minimize the number of clock buffers switching and the clock
network capacitance
• Minimize capacitance on high frequency logic
• Isolate high activity logic to reduce interconnect length
• Isolate memory with high frequency access
• Minimize unnecessary switching and eliminate glitches.

I suppose the EPLD maybe a better solution. MaxII have more LE than normal EPLD and less power. So you may see if this chip fit for you.
Best Regards.

"So out the question to put them on a satellite !
so any documents that you can advice?? "

if u want to use them in space also look at the effects of cosmic readiation.
u will need redhard devices. i do not think fpga and cpld are available in redhard version.
on a second thought actel may have it as they use flesh version.
hock

hi folks

that is very true. fpga is the best solution for the portable desines as the time required for the development is very small. as far as the power consumption is concerned i would say that compared to asics it consues a little larger but still managable.


regards
ashish

Hi guys,

I was quite surprise to see how much power you can save with a good VHDL/Verilog coding style. Of course the technology you are targeting is important, the lower the core voltage the better.

I was involved in the design of a telecomms handheld with Sp@rtan3 devices. I used XPower stuff from Xilinx to estimate everything, not bad. It can give you a rough idea of the power you can save with different designs, the problem is that it uses the .ncd file and the output of your simulator, hard work Of course your best friend will be the clock, reducing the frequency will reduce the dynamic power by a long chunk. People talk about gating the clock...uhmm! don't like it, but you might have to do that, again it depends of your application. Grey coding for counters and FSMs. A very good idea is to have different FPGA images stored in flash for example, images with specific functionality such that...if the user presses button A then download image with A functionality, if it presses B the same and so on.

As you know, the Coolrunner family is a nice solution for power hungry application. They are tiny though, it depends of your application, don't expect to fit in a Coolrunner an OC-3 deframer for example 8O

Regards,

-maestor

i'm from germany, here is a magazine available which is called makt&technik (keeps you on track of all new inventions and plans of vendors, everything very short, more for sales guys, but not bad). in the last magazine (if i remember right) was just an article about the question of eltonjohn. there are smaller vendors, who are planning to develope new fpgas with little power consumption. if there are some people who are interested in this article (maybe 5 or more) i offer to translate this article. send me a pm.
regards, ep20k.

hi
as i know the high price ofit let you not to do
the job with fpga
bye

I have to mention that
FPGA can consume amperes
when it is switshed on, resetted and the configuration process is in progress.
This period is rather short, and the energy is little, but
the power circuit must provide these amperes.
In another circumstances, for example, Xilinx does not sure
the correct configuration.
As to radiation
then FPGAs are well protected against it, and they have immunity that
1-2 degrees of magnitude higher than CPLD, EEPROM have.

Coolrunner is a good choice, runs on potatoes

Well is not TRUE .. First Coolrunner are very small the big one is only 512 macros or the equivalent of 12k gates .. They run on POTATOS if you don't do a thing ! otherwise the data sheet indicates that using all the cells at the same time at 120Mhz it requires 300mA at 3 volts .. that's 1 watt
but it appears that power consuption is linear .So in order to keep the power low you have to use just a small fraction or to lower the frequency .
So to implement a cpu this is not a good idea .I'm looking to implement a particuliar Cpu on a fpga for portable application . This won't work!
next ...

Have you ever looked at Actel FPGAs?

At least they mention their FPGAs running in handheld devices.
Maybe the new series coming out this year or Q1/2005 might be even better.