Is it possible to navigate through a path automatically in Vivado ?

[msdarvishi]

Dear all,

I am using Vivado 2015.4 and trying to create antenna effect (parasitic line added to the main path) after full placement&routing. On each large switch box, once we do click on any PIP (circles associated with each switch box) it shows all the PIPs and possible wires connected to that PIP. I am sure that once we do click on each PIP, Vivado will execute a command in Tcl console that provides us the full list of PIPs and wires connected to that PIP. But this command is hidden from user and it is not accessible !!! Does anyone know is it possible to obtain that command or even is it possible to have a Tcl script that navigates through a path and automatically determines the list of possible wires connected to a PIP?

I think something that is missing here is ONLY that command that Vivado executes to provide the PIPs list.

Kind replies and helps are cordially appreciated.

Regards,

- - - Updated - - -

Please have a look to a snapshop from Vivado where doing a click on each PIP provides the list of all PIPs and wires connected to it. I am looking for that command in Tcl that provides this list !

- - - Updated - - -

At least if we can a Tcl script somehow to extract the PIPs and wires associated with ONLY the PIP that I have clicked, it worth too much.

- - - Updated - - -

REMARK : I see the list is provided in PIP Junctions Tab when we do click on whole Switch box (see attached photo). But how to perform a command in Tcl in order to extract the PIP junctions ??

 

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Using the following command on a 7K325

get_nodes -downhill -of_objects [get_nodes CLBLM_R_X11Y158/CLBLM_LOGIC_OUTS21]

This produces the following list of node objects:

INT_R_X11Y158/IMUX7 INT_R_X11Y158/IMUX39 INT_R_X11Y158/IMUX47 INT_R_X11Y158/FAN_ALT3 INT_R_X11Y158/BYP_ALT7 INT_R_X11Y158/IMUX31 INT_R_X11Y158/IMUX15 INT_R_X11Y158/IMUX23 INT_R_X11Y158/SS2BEG3 INT_R_X11Y158/SS6BEG3 INT_R_X11Y158/SW2BEG3 INT_R_X11Y158/WR1BEG_S0 INT_R_X11Y158/SW6BEG3 INT_R_X11Y158/WL1BEG2 INT_R_X11Y158/NL1BEG2 INT_R_X11Y158/WW4BEG3 INT_R_X11Y158/EE2BEG3 INT_R_X11Y158/SE2BEG3 INT_R_X11Y158/NE6BEG3 INT_R_X11Y158/NR1BEG3 INT_R_X11Y158/NN6BEG3 INT_R_X11Y158/NW2BEG3 INT_R_X11Y158/NN2BEG3 INT_R_X11Y158/NW6BEG3 INT_R_X11Y158/NE2BEG3 INT_R_X11Y158/ER1BEG_S0 INT_R_X11Y158/SL1BEG3 INT_R_X11Y158/SR1BEG_S0 INT_R_X11Y158/EE4BEG3 INT_R_X11Y158/WW2BEG3 INT_R_X11Y158/SE6BEG3 INT_R_X11Y158/EL1BEG2

Which matches the spot checked nodes on the switch matrix, from that source node.

Here is a picture of the selected node and the switchboxes it is attached to the large one on the left is the connections shown in the above list.


- - - Updated - - -

If you use uphill instead of downhill you'll get the output of the CLBLM_M_BMUX.

You should really sit down and read UG835 and play around with an open design trying out the commands and see what you can learn. That's the only reason I suspected their might be a way to do this as I recalled the get_nodes command would output these types of items.

 

[msdarvishi]

Using the following command on a 7K325

get_nodes -downhill -of_objects [get_nodes CLBLM_R_X11Y158/CLBLM_LOGIC_OUTS21]

This produces the following list of node objects:

INT_R_X11Y158/IMUX7 INT_R_X11Y158/IMUX39 INT_R_X11Y158/IMUX47 INT_R_X11Y158/FAN_ALT3 INT_R_X11Y158/BYP_ALT7 INT_R_X11Y158/IMUX31 INT_R_X11Y158/IMUX15 INT_R_X11Y158/IMUX23 INT_R_X11Y158/SS2BEG3 INT_R_X11Y158/SS6BEG3 INT_R_X11Y158/SW2BEG3 INT_R_X11Y158/WR1BEG_S0 INT_R_X11Y158/SW6BEG3 INT_R_X11Y158/WL1BEG2 INT_R_X11Y158/NL1BEG2 INT_R_X11Y158/WW4BEG3 INT_R_X11Y158/EE2BEG3 INT_R_X11Y158/SE2BEG3 INT_R_X11Y158/NE6BEG3 INT_R_X11Y158/NR1BEG3 INT_R_X11Y158/NN6BEG3 INT_R_X11Y158/NW2BEG3 INT_R_X11Y158/NN2BEG3 INT_R_X11Y158/NW6BEG3 INT_R_X11Y158/NE2BEG3 INT_R_X11Y158/ER1BEG_S0 INT_R_X11Y158/SL1BEG3 INT_R_X11Y158/SR1BEG_S0 INT_R_X11Y158/EE4BEG3 INT_R_X11Y158/WW2BEG3 INT_R_X11Y158/SE6BEG3 INT_R_X11Y158/EL1BEG2

Which matches the spot checked nodes on the switch matrix, from that source node.

Here is a picture of the selected node and the switchboxes it is attached to the large one on the left is the connections shown in the above list.
View attachment 137415

- - - Updated - - -

If you use uphill instead of downhill you'll get the output of the CLBLM_M_BMUX.

You should really sit down and read UG835 and play around with an open design trying out the commands and see what you can learn. That's the only reason I suspected their might be a way to do this as I recalled the get_nodes command would output these types of items.

EXACTLY ! Thank you. This is mine as well:

get_nodes -downhill -of_objects [get_nodes CLBLL_L_X2Y51/CLBLL_LOGIC_OUTS5

that produces the following PIPs list:

INT_L_X2Y51/IMUX_L18 INT_L_X2Y51/IMUX_L10 INT_L_X2Y51/IMUX_L2 INT_L_X2Y51/FAN_ALT2 INT_L_X2Y51/IMUX_L42 INT_L_X2Y51/IMUX_L34 INT_L_X2Y51/IMUX_L26 INT_L_X2Y51/BYP_ALT4 INT_L_X2Y51/NE6BEG1 INT_L_X2Y51/EE2BEG1 INT_L_X2Y51/SE2BEG1 INT_L_X2Y51/NL1BEG0 INT_L_X2Y51/WW4BEG1 INT_L_X2Y51/WL1BEG0 INT_L_X2Y51/SW2BEG1 INT_L_X2Y51/SS6BEG1 INT_L_X2Y51/SS2BEG1 INT_L_X2Y51/SR1BEG2 INT_L_X2Y51/SE6BEG1 INT_L_X2Y51/SW6BEG1 INT_L_X2Y51/NE2BEG1 INT_L_X2Y51/SL1BEG1 INT_L_X2Y51/NN2BEG1 INT_L_X2Y51/EE4BEG1 INT_L_X2Y51/ER1BEG2 INT_L_X2Y51/NW2BEG1 INT_L_X2Y51/NN6BEG1 INT_L_X2Y51/EL1BEG0 INT_L_X2Y51/NR1BEG1 INT_L_X2Y51/WW2BEG1 INT_L_X2Y51/NW6BEG1 INT_L_X2Y51/WR1BEG2

Just as a remark for the future designers and visitors, the statement written after get_nodes command is exactly the Name of the wire connected to a specific PIP to the large switch box that is our desired to extract all its associated wires.

 

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Just as a remark for the future designers and visitors, the statement written after get_nodes command is exactly the Name of the wire connected to a specific PIP to the large switch box that is our desired to extract all its associated wires.

Good that you pointed this out. I probably should have mentioned this myself, but I'm so used to messing around with the Tcl command to extract stuff that sometimes I forget not everyone uses Tcl commands to control Vivado or find stuff in the design.

 

[msdarvishi]

Dear @ads-ee,

Relying on the procedure that you've mentioned, I found another useful way to extract those PIPs using the following command. I put this for future visitors to facilitate achieving their goals:

get_pips -downhill -of_objects [get_nodes CLBLL_L_X2Y51/CLBLL_LOGIC_OUTS5]

that provides the following outputs that matched the spot list as well:

INT_L_X2Y51/INT_L.LOGIC_OUTS_L5->>WW4BEG1 INT_L_X2Y51/INT_L.LOGIC_OUTS_L5->>WW2BEG1 INT_L_X2Y51/INT_L.LOGIC_OUTS_L5->>WR1BEG2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L5->>SW6BEG1 INT_L_X2Y51/INT_L.LOGIC_OUTS_L5->>SW2BEG1 INT_L_X2Y51/INT_L.LOGIC_OUTS_L5->>SS6BEG1 INT_L_X2Y51/INT_L.LOGIC_OUTS_L5->>SS2BEG1 INT_L_X2Y51/INT_L.LOGIC_OUTS_L5->>SR1BEG2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L5->>SL1BEG1 INT_L_X2Y51/INT_L.LOGIC_OUTS_L5->>SE6BEG1 INT_L_X2Y51/INT_L.LOGIC_OUTS_L5->>SE2BEG1 INT_L_X2Y51/INT_L.LOGIC_OUTS_L5->>BYP_ALT4 INT_L_X2Y51/INT_L.LOGIC_OUTS_L5->>FAN_ALT2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L5->>NW6BEG1 INT_L_X2Y51/INT_L.LOGIC_OUTS_L5->>NW2BEG1 INT_L_X2Y51/INT_L.LOGIC_OUTS_L5->>NR1BEG1 INT_L_X2Y51/INT_L.LOGIC_OUTS_L5->>NN6BEG1 INT_L_X2Y51/INT_L.LOGIC_OUTS_L5->>NN2BEG1 INT_L_X2Y51/INT_L.LOGIC_OUTS_L5->>NE6BEG1 INT_L_X2Y51/INT_L.LOGIC_OUTS_L5->>NE2BEG1 INT_L_X2Y51/INT_L.LOGIC_OUTS_L5->>IMUX_L42 INT_L_X2Y51/INT_L.LOGIC_OUTS_L5->>IMUX_L34 INT_L_X2Y51/INT_L.LOGIC_OUTS_L5->>IMUX_L2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L5->>IMUX_L26 INT_L_X2Y51/INT_L.LOGIC_OUTS_L5->>IMUX_L18 INT_L_X2Y51/INT_L.LOGIC_OUTS_L5->>IMUX_L10 INT_L_X2Y51/INT_L.LOGIC_OUTS_L5->>ER1BEG2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L5->>EE4BEG1 INT_L_X2Y51/INT_L.LOGIC_OUTS_L5->>EE2BEG1 INT_L_X2Y51/INT_L.LOGIC_OUTS_L5->>WL1BEG0 INT_L_X2Y51/INT_L.LOGIC_OUTS_L5->>NL1BEG0 INT_L_X2Y51/INT_L.LOGIC_OUTS_L5->>EL1BEG0

 

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I see this also gives the added pip name on the path ->>WW4BEG1 for the first node.

So is this just a continuation of your directed routing efforts from a previous thread on Problem with "find_routing_path" command in Tcl?

If so you might consider producing a how to on directed routing for Xilinx parts in the blog section of edaboard. If nothing else you'll have a reference to go back to when you haven't done it for month or two.

 

[msdarvishi]

Dear all,

I am using Vivado 2015.4 and trying to create antenna effect (parasitic line added to the main path) after full placement&routing. On each large switch box, once we do click on any PIP (circles associated with each switch box) it shows all the PIPs and possible wires connected to that PIP. I am sure that once we do click on each PIP, Vivado will execute a command in Tcl console that provides us the full list of PIPs and wires connected to that PIP. But this command is hidden from user and it is not accessible !!! Does anyone know is it possible to obtain that command or even is it possible to have a Tcl script that navigates through a path and automatically determines the list of possible wires connected to a PIP?

I think something that is missing here is ONLY that command that Vivado executes to provide the PIPs list.

Kind replies and helps are cordially appreciated.

Regards,

- - - Updated - - -

Please have a look to a snapshop from Vivado where doing a click on each PIP provides the list of all PIPs and wires connected to it. I am looking for that command in Tcl that provides this list !View attachment 137413

- - - Updated - - -

At least if we can a Tcl script somehow to extract the PIPs and wires associated with ONLY the PIP that I have clicked, it worth too much.

- - - Updated - - -

REMARK : I see the list is provided in PIP Junctions Tab when we do click on whole Switch box (see attached photo). But how to perform a command in Tcl in order to extract the PIP junctions ??

kaDear all,

I would like to obtain the number of PIPs and wires associated with a specific PIP in my design as shown in the initial figure of this post. To achieve that, I wrote the following commands in Tcl console:

get_pips -downhill -of_objects [get_nodes CLBLL_L_X2Y51/CLBLL_LOGIC_OUTS20]

that produces the following result:

INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WW4BEG2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WW2BEG2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WR1BEG3 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>SW6BEG2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>SW2BEG2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>SS6BEG2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>SS2BEG2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>SR1BEG3 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>SL1BEG2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>SE6BEG2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>SE2BEG2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>BYP_ALT2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>FAN_ALT7 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>NW6BEG2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>NW2BEG2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>NR1BEG2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>NN6BEG2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>NN2BEG2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>NE6BEG2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>NE2BEG2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>IMUX_L4 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>IMUX_L44 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>IMUX_L36 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>IMUX_L28 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>IMUX_L20 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>IMUX_L12 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>ER1BEG3 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>EE4BEG2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>EE2BEG2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WL1BEG1 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>NL1BEG1 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>EL1BEG1

Now, I want to put these results in a list (or array, I do not know which one is correct to say?) and create a loop and call the elements of that list (or array) one by one. All the trials that I have done were failed ! Can anyone help me how to go with this issue?

Kind replies and helps are cordially appreciated.

Thanks,

 

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try looking at foreach, I think that might do the trick. https://wiki.tcl.tk/1018

e.g.

foreach a [get_pips -downhill -of_objects [get_nodes CLBLL_L_X2Y51/CLBLL_LOGIC_OUTS20]] {puts "$a"}

will list out each object in the list on a separate line.

BTW, I've verified that this does work on my test design.

- - - Updated - - -

All the trials that I have done were failed ! Can anyone help me how to go with this issue?

In the future please post what you tried and how it fails, might be helpful for you if someone more familiar with Tcl can tell you why it fails, so you'll understand how to use Tcl better.

 

[msdarvishi]

try looking at foreach, I think that might do the trick. https://wiki.tcl.tk/1018

e.g.

foreach a [get_pips -downhill -of_objects [get_nodes CLBLL_L_X2Y51/CLBLL_LOGIC_OUTS20]] {puts "$a"}

will list out each object in the list on a separate line.

BTW, I've verified that this does work on my test design.

- - - Updated - - -


In the future please post what you tried and how it fails, might be helpful for you if someone more familiar with Tcl can tell you why it fails, so you'll understand how to use Tcl better.

Dear @ads-ee,

Thanks for your kind reply. I used the foreach command and I found new things. I created a list named piplist and then, I used a for loop in order to print each pip associated in the list with its number. See below please:

list piplist [get_pips -downhill -of_objects [get_nodes CLBLL_L_X2Y51/CLBLL_LOGIC_OUTS20]]

for {set i 1} {$i <= [llength [get_pips -downhill -of_objects [get_nodes CLBLL_L_X2Y51/CLBLL_LOGIC_OUTS20]]]} {incr i} {
	puts "pip $i is $piplist"
}

this code results in the following outputs:

pip 1 is INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WW4BEG2
pip 2 is INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WW4BEG2
pip 3 is INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WW4BEG2
pip 4 is INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WW4BEG2
pip 5 is INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WW4BEG2
pip 6 is INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WW4BEG2
pip 7 is INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WW4BEG2
pip 8 is INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WW4BEG2
pip 9 is INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WW4BEG2
pip 10 is INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WW4BEG2
pip 11 is INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WW4BEG2
pip 12 is INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WW4BEG2
pip 13 is INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WW4BEG2
pip 14 is INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WW4BEG2
pip 15 is INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WW4BEG2
pip 16 is INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WW4BEG2
pip 17 is INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WW4BEG2
pip 18 is INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WW4BEG2
pip 19 is INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WW4BEG2
pip 20 is INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WW4BEG2
pip 21 is INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WW4BEG2
pip 22 is INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WW4BEG2
pip 23 is INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WW4BEG2
pip 24 is INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WW4BEG2
pip 25 is INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WW4BEG2
pip 26 is INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WW4BEG2
pip 27 is INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WW4BEG2
pip 28 is INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WW4BEG2
pip 29 is INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WW4BEG2
pip 30 is INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WW4BEG2
pip 31 is INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WW4BEG2
pip 32 is INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WW4BEG2

So, amazingly, as we see, only the first element of piplist is printed out for the incremental numbers while the piplist itsels contains the follwing PIPs:

get_pips -downhill -of_objects [get_nodes CLBLL_L_X2Y51/CLBLL_LOGIC_OUTS20]

that returns:

[COLOR="#FF0000"]INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WW4BEG2[/COLOR] INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WW2BEG2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WR1BEG3 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>SW6BEG2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>SW2BEG2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>SS6BEG2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>SS2BEG2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>SR1BEG3 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>SL1BEG2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>SE6BEG2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>SE2BEG2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>BYP_ALT2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>FAN_ALT7 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>NW6BEG2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>NW2BEG2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>NR1BEG2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>NN6BEG2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>NN2BEG2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>NE6BEG2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>NE2BEG2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>IMUX_L4 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>IMUX_L44 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>IMUX_L36 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>IMUX_L28 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>IMUX_L20 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>IMUX_L12 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>ER1BEG3 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>EE4BEG2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>EE2BEG2 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WL1BEG1 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>NL1BEG1 INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>EL1BEG1

in the precedent code, only the RED highlighted element that is the first one is sent to the output ! I do not know how can we update the piplist for each iteration?


Thanks and Regards,

- - - Updated - - -

Dear @ads-ee,

Meanwhile that I put my previous problem here, I did some trials and I could solve this problem. However, I do not delete my previous problem to let the future designers how it can be solved if they encounter this problem.

In order to call each element of created list with name of piplist, i used the following proc along with the foreach command that you have already suggested:

proc PIPs { } {
set piplist [get_pips -downhill -of_objects [get_nodes CLBLL_L_X2Y51/CLBLL_LOGIC_OUTS20]]
set i 1
foreach j $piplist {
    puts "The $i th PIP is   $j"
    incr i
}
}

PIPs

executing this proc in Tcl console returns the following outputs, that exactly matches the objective of the previous problem :clap:

The 1 th PIP is   INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WW4BEG2
The 2 th PIP is   INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WW2BEG2
The 3 th PIP is   INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WR1BEG3
The 4 th PIP is   INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>SW6BEG2
The 5 th PIP is   INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>SW2BEG2
The 6 th PIP is   INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>SS6BEG2
The 7 th PIP is   INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>SS2BEG2
The 8 th PIP is   INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>SR1BEG3
The 9 th PIP is   INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>SL1BEG2
The 10 th PIP is   INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>SE6BEG2
The 11 th PIP is   INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>SE2BEG2
The 12 th PIP is   INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>BYP_ALT2
The 13 th PIP is   INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>FAN_ALT7
The 14 th PIP is   INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>NW6BEG2
The 15 th PIP is   INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>NW2BEG2
The 16 th PIP is   INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>NR1BEG2
The 17 th PIP is   INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>NN6BEG2
The 18 th PIP is   INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>NN2BEG2
The 19 th PIP is   INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>NE6BEG2
The 20 th PIP is   INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>NE2BEG2
The 21 th PIP is   INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>IMUX_L4
The 22 th PIP is   INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>IMUX_L44
The 23 th PIP is   INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>IMUX_L36
The 24 th PIP is   INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>IMUX_L28
The 25 th PIP is   INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>IMUX_L20
The 26 th PIP is   INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>IMUX_L12
The 27 th PIP is   INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>ER1BEG3
The 28 th PIP is   INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>EE4BEG2
The 29 th PIP is   INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>EE2BEG2
The 30 th PIP is   INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WL1BEG1
The 31 th PIP is   INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>NL1BEG1
The 32 th PIP is   INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>EL1BEG1

I have to cordially appreciate for the foreach command suggestion that made the was forward !

Regards,

 

[ads-ee]

To use your original for loop you would have had to add an lindex to extract each item returned by your get_pips command. As this happens a lot the foreach command is available to make it simpler.

 

[msdarvishi]

To use your original for loop you would have had to add an lindex to extract each item returned by your get_pips command. As this happens a lot the foreach command is available to make it simpler.

Dear @ads-ee,

Concerning the solution made in this post, Now when I am trying to connect the wires associated with the pip (CLBLL_LOGIC_OURS20) one-by-one using a loop as follows, indeed I will need the name of the second PIP junction to be used in a loop, nor the whole name of the extracted wire. For example, using the foreach loop above gives the wires list as shown above (from number 1 to 32) as INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>EL1BEG1 where it includes the tile name (INT_L_X2Y51), then the first PIP junction name (INT_L.LOGIC_OUTS_L20), and finally the name of the second PIP junction (ELE1BEG1). In my following loop I will need only the name of the second PIP junction to be added to the routing and I do not know how to extract only the second PIP junction from my list??!!

proc PIPs { } {
set piplist [get_pips -downhill -of_objects [get_nodes CLBLL_L_X2Y51/CLBLL_LOGIC_OUTS20]]
for { set i 0 } {$i < [llength $piplist] } { incr i} { 
	    puts "The $i th PIP is [lindex $piplist $i]"
	    set_property FIXED_ROUTE { { CLBLL_LL_AMUX CLBLL_LOGIC_OUTS20   {IMUX_L4  CLBLL_LL_A6}   [COLOR="#FF0000"]ER1BEG3[/COLOR] } } [get_nets Inst_StartPoint_DFF/Qs]
}
}

PIPs

Please look at the red-highlighted name above. That is the second PIP junction name of the following wire connected to the PIP extracted from the list in the precedent post as follows:

The 27 th PIP is INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>ER1BEG3

Do you have any idea and comment?

Thanks and Regards,

 

[ads-ee]

use that lindex command I mentioned in a previous post:

e.g. lindex {a b c d e} 2
will return c

Note: indices into the list are 0 based.

Seems you are having more problems with Tcl than the Xilinx tools, might be worthwhile to pick up a Tcl reference.

- - - Updated - - -

Opps, I just realize you wanted the second red text EL1BEG1 extracted. Well you could use a regular expression as the result of the lindex you use to get that entire line is a string.

Something like this will grab the name.

% regex {.*>>(.*)} INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>EL1BEG1 match sub1
% puts $sub1

will output EL1BEG1

Though I admit there is probably a more elegant approach. If you need the first part and the second part then this should work.

% regex {(.*)->>(.*)} INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>EL1BEG1 match first second
% puts "$first   $second"

which will output INT_L_X2Y51/INT_L.LOGIC_OUTS_L20 EL1BEG1

 

[msdarvishi]

use that lindex command I mentioned in a previous post:

e.g. lindex {a b c d e} 2
will return c

Note: indices into the list are 0 based.

Seems you are having more problems with Tcl than the Xilinx tools, might be worthwhile to pick up a Tcl reference.

- - - Updated - - -

Opps, I just realize you wanted the second red text EL1BEG1 extracted. Well you could use a regular expression as the result of the lindex you use to get that entire line is a string.

Something like this will grab the name.

% regex {.*>>(.*)} INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>EL1BEG1 match sub1
% puts $sub1

will output EL1BEG1

Though I admit there is probably a more elegant approach. If you need the first part and the second part then this should work.

% regex {(.*)->>(.*)} INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>EL1BEG1 match first second
% puts "$first   $second"

which will output INT_L_X2Y51/INT_L.LOGIC_OUTS_L20 EL1BEG1

Dear @ads-ee,

Thank you for your kind reply and explanation. I agree with you that most of my problems come from Tcl coding nor the Xilinx tools !

Just to ensure that your hint is working, I just added the following lines in my loop and resulted the following outputs that exactly match what I want :lol:

regex {.*>>(.*)} INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>$j match sub1
    puts $sub1

Result:

WW4BEG2
WW2BEG2
WR1BEG3
SW6BEG2
SW2BEG2
SS6BEG2
SS2BEG2
SR1BEG3
SL1BEG2
SE6BEG2
SE2BEG2
BYP_ALT2
FAN_ALT7
NW6BEG2
NW2BEG2
NR1BEG2
NN6BEG2
NN2BEG2
NE6BEG2
NE2BEG2
IMUX_L4
IMUX_L44
IMUX_L36
IMUX_L28
IMUX_L20
IMUX_L12
ER1BEG3
EE4BEG2
EE2BEG2
WL1BEG1
NL1BEG1
EL1BEG1

Thanks for your care and assist.

 

[ads-ee]

I find it amazing that nobody else seems to have been helping you in this thread...Hard to believe that no one besides me knows Tcl well enough to help. :shock:

I'm glad I've been of assistance, what you are doing seems rather interesting. Could you explain why you want to hand route (scripted route) a design? Is this some critical placement and routing that you need to keep from run to run?

 

[msdarvishi]

I find it amazing that nobody else seems to have been helping you in this thread...Hard to believe that no one besides me knows Tcl well enough to help. :shock:

I'm glad I've been of assistance, what you are doing seems rather interesting. Could you explain why you want to hand route (scripted route) a design? Is this some critical placement and routing that you need to keep from run to run?

Thank you @ads-ee for your reply. Yes, absolutely, Io want to check some routing criticals from run to run.

Fortunately, the list of second PIP junctions were extracted by those codes. But while I try to add them one-by- one to the main routing, it does not work ! I used the following loop:

proc PIPs { } {
set piplist [get_pips -downhill -of_objects [get_nodes CLBLL_L_X2Y51/CLBLL_LOGIC_OUTS20]]
set i 1
foreach j $piplist {
    regex {.*>>(.*)} INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>$j match sub1
    puts $sub1
    set_property FIXED_ROUTE { { CLBLL_LL_AMUX CLBLL_LOGIC_OUTS20   {IMUX_L4  CLBLL_LL_A6}   $sub1 } } [get_nets Inst_StartPoint_DFF/Qs]
    incr i
}
}

PIPs

that gives the following error after execution:

[COLOR="#FF0000"]ERROR: [Designutils 20-941] Did not find node resource, $sub1, downhill from node, CLBLL_L_X2Y51/CLBLL_LOGIC_OUTS20.
Downhill node choices include:  INT_L_X2Y51/WW4BEG2 INT_L_X2Y51/WW2BEG2 INT_L_X2Y51/WR1BEG3 INT_L_X2Y51/SW6BEG2 INT_L_X2Y51/SW2BEG2 INT_L_X2Y51/SS6BEG2 INT_L_X2Y51/SS2BEG2 INT_L_X2Y51/SR1BEG3 INT_L_X2Y51/SL1BEG2 INT_L_X2Y51/SE6BEG2 INT_L_X2Y51/SE2BEG2 INT_L_X2Y51/BYP_ALT2 INT_L_X2Y51/FAN_ALT7 INT_L_X2Y51/NW6BEG2 INT_L_X2Y51/NW2BEG2 INT_L_X2Y51/NR1BEG2 INT_L_X2Y51/NN6BEG2 INT_L_X2Y51/NN2BEG2 INT_L_X2Y51/NE6BEG2 INT_L_X2Y51/NE2BEG2 INT_L_X2Y51/IMUX_L4 INT_L_X2Y51/IMUX_L44 INT_L_X2Y51/IMUX_L36 INT_L_X2Y51/IMUX_L28 INT_L_X2Y51/IMUX_L20 INT_L_X2Y51/IMUX_L12 INT_L_X2Y51/ER1BEG3 INT_L_X2Y51/EE4BEG2 INT_L_X2Y51/EE2BEG2 INT_L_X2Y51/WL1BEG1 INT_L_X2Y51/NL1BEG1 INT_L_X2Y51/EL1BEG1 .[/COLOR]

I do not know which part does not work propoerly !!!

Thanks and Regards,

 

[ads-ee]

foreach j $piplist {
    regex {.*>>(.*)} INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>$j match sub1

What you are doing here is performing a regex on the following string:

INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WW4BEG2

Which happens to still work as the first .* is greedy and gobbles up everything including the first instance of >> before stopping on the second instance of >>.

The primary issue appears to be that the resulting node resource it wants to see is in the form:

INIT_L_X2Y51/WW4BEG2

See your red error message for what it was expecting, this is not what you generate in the loop for sub1.

Try something more like this:

proc PIPs { } {
  set piplist [get_pips -downhill -of_objects [get_nodes CLBLL_L_X2Y51/CLBLL_LOGIC_OUTS20]]
  set i 1
  foreach j $piplist {
    regex {.*>>(.*)} $j match sub1
    set_property FIXED_ROUTE { { CLBLL_LL_AMUX CLBLL_LOGIC_OUTS20   {IMUX_L4  CLBLL_LL_A6}  INT_L_X2Y51/$sub1 } } [get_nets Inst_StartPoint_DFF/Qs]
    incr i
  }
}

You first extract the sub1 string (e.g. W4BEG2 for the first pip) then append it to the INT_L_X2Y51/<pip_name>. You might have to play around with that, as I can't check it without the design checkpoint.

 

[msdarvishi]

foreach j $piplist {
    regex {.*>>(.*)} INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>$j match sub1

What you are doing here is performing a regex on the following string:

INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>INT_L_X2Y51/INT_L.LOGIC_OUTS_L20->>WW4BEG2

Which happens to still work as the first .* is greedy and gobbles up everything including the first instance of >> before stopping on the second instance of >>.

The primary issue appears to be that the resulting node resource it wants to see is in the form:

INIT_L_X2Y51/WW4BEG2

See your red error message for what it was expecting, this is not what you generate in the loop for sub1.

Try something more like this:

proc PIPs { } {
  set piplist [get_pips -downhill -of_objects [get_nodes CLBLL_L_X2Y51/CLBLL_LOGIC_OUTS20]]
  set i 1
  foreach j $piplist {
    regex {.*>>(.*)} $j match sub1
    set_property FIXED_ROUTE { { CLBLL_LL_AMUX CLBLL_LOGIC_OUTS20   {IMUX_L4  CLBLL_LL_A6}  INT_L_X2Y51/$sub1 } } [get_nets Inst_StartPoint_DFF/Qs]
    incr i
  }
}

You first extract the sub1 string (e.g. W4BEG2 for the first pip) then append it to the INT_L_X2Y51/<pip_name>. You might have to play around with that, as I can't check it without the design checkpoint.

Dear ads-ee,

Thanks for your reply and explanation. I did lots of trials with the hint that you have mentioned in your last post and played around it too much, but always it returns the same error message. I have the design checkpoint in the attachment, Is it possible to have a look on that, please? I sincerely appreciate it.View attachment checkpoint_1.rar
Since uploading a .dcp file was not possible here, I made a RAR file.

Thanks and Regards,

 

[ads-ee]

The problem stems from Tcl not substituting the value of sub1 into the fixed_route DIRT string as that string is inside {}, which does not allow variable substitution. As I couldn't find a method to force the variable substitution I resorted to play "tricks" with creating the DIRT string before hand and then letting variable substitution occur in the set_property command.

Here are the steps I used.

# first create a dirt_str without the variable substitution string.
[COLOR="#0000FF"]set dirt_str { CLBLL_LL_AMUX CLBLL_LOGIC_OUTS20   {IMUX_L4  CLBLL_LL_A6} }[/COLOR]
[I]>>>  CLBLL_LL_AMUX CLBLL_LOGIC_OUTS20   {IMUX_L4  CLBLL_LL_A6} [/I]

# now append the substitution string...(FYI you didn't need the INT_L_X2Y51/ stuff)
[COLOR="#0000FF"]lappend dirt_str $sub1[/COLOR]
[I]>>> CLBLL_LL_AMUX CLBLL_LOGIC_OUTS20 {IMUX_L4  CLBLL_LL_A6} WW4BEG2[/I]

# not sure this is necessary but if the {{ dirt_string_entires }} double curly brackets are required... (Note, I could get the command to work with only a single set). Add the following:
[COLOR="#0000FF"]lappend {} $dirt_str[/COLOR]
[I]>>> {CLBLL_LL_AMUX CLBLL_LOGIC_OUTS20 {IMUX_L4  CLBLL_LL_A6} WW4BEG2}[/I]

# then use the new $dirt_str
[COLOR="#0000FF"]set_property FIXED_ROUTE $dirt_str [get_nets Inst_StartPoint_DFF/Qs][/COLOR]

- - - Updated - - -

Okay never mind the convoluted way I did above here is a much simpler way to do it. Needed to use better google-fu. ;-)

# In a one liner, use the list function to create the list as that will force variable substitution.
set_property FIXED_ROUTE [list [list CLBLL_LL_AMUX CLBLL_LOGIC_OUTS20 {IMUX_L4  CLBLL_LL_A6} $sub1]] [get_nets Inst_StartPoint_DFF/Qs][COLOR="#0000FF"][/COLOR]

The list commands generate the following list:
{ {CLBLL_LL_AMUX CLBLL_LOGIC_OUTS20 {IMUX_L4 CLBLL_LL_A6} WW4BEG2} }

As previously stated only use the double list if it's absolutely mandatory, didn't appear to be to me.

 

[msdarvishi]

The problem stems from Tcl not substituting the value of sub1 into the fixed_route DIRT string as that string is inside {}, which does not allow variable substitution. As I couldn't find a method to force the variable substitution I resorted to play "tricks" with creating the DIRT string before hand and then letting variable substitution occur in the set_property command.

Here are the steps I used.

# first create a dirt_str without the variable substitution string.
[COLOR="#0000FF"]set dirt_str { CLBLL_LL_AMUX CLBLL_LOGIC_OUTS20   {IMUX_L4  CLBLL_LL_A6} }[/COLOR]
[I]>>>  CLBLL_LL_AMUX CLBLL_LOGIC_OUTS20   {IMUX_L4  CLBLL_LL_A6} [/I]

# now append the substitution string...(FYI you didn't need the INT_L_X2Y51/ stuff)
[COLOR="#0000FF"]lappend dirt_str $sub1[/COLOR]
[I]>>> CLBLL_LL_AMUX CLBLL_LOGIC_OUTS20 {IMUX_L4  CLBLL_LL_A6} WW4BEG2[/I]

# not sure this is necessary but if the {{ dirt_string_entires }} double curly brackets are required... (Note, I could get the command to work with only a single set). Add the following:
[COLOR="#0000FF"]lappend {} $dirt_str[/COLOR]
[I]>>> {CLBLL_LL_AMUX CLBLL_LOGIC_OUTS20 {IMUX_L4  CLBLL_LL_A6} WW4BEG2}[/I]

# then use the new $dirt_str
[COLOR="#0000FF"]set_property FIXED_ROUTE $dirt_str [get_nets Inst_StartPoint_DFF/Qs][/COLOR]

- - - Updated - - -

Okay never mind the convoluted way I did above here is a much simpler way to do it. Needed to use better google-fu. ;-)

# In a one liner, use the list function to create the list as that will force variable substitution.
set_property FIXED_ROUTE [list [list CLBLL_LL_AMUX CLBLL_LOGIC_OUTS20 {IMUX_L4  CLBLL_LL_A6} $sub1]] [get_nets Inst_StartPoint_DFF/Qs][COLOR="#0000FF"][/COLOR]

The list commands generate the following list:
{ {CLBLL_LL_AMUX CLBLL_LOGIC_OUTS20 {IMUX_L4 CLBLL_LL_A6} WW4BEG2} }

As previously stated only use the double list if it's absolutely mandatory, didn't appear to be to me.

Dear @ads-ee,

Thank you so much ! It is supper ! Now the problem gt solved with your hint

Regards,