Is it possible to have a zero skew in a design?

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Re: Zero skew?

practically we cant reduce any delay to zero.... delay will exist... hence we try to make skew "equal" (or same) rather than "zero"......now with this optimization all flops get the clock edge with same delay relative to each other.... so virtually we can say they are having "zero skew " or skew is "balanced".

rgds
https://asic-soc.blogspot.com
 

Zero skew?

well, Theorotically yes, it is possible to get design with zero skew. and practically can't say, yes and no both. lets consider that we can not reduce path delay, but we can intentionaly add delay to some path in order to get zero skew, depents how accurately u r modeling the RC component in path.
Also, the path delay can be reduced, as it is not only depends on track/ wire length but also on its width and thickness.
 
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