Is it possible to do conditional port mapping in VHDL??

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saurabh252

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I want to make parallel in serial out shift register using structural modeling..
in that i have made d-ff with reset ,load ,clk,data_in,data_out..
now in shift register i have to make code such that when ever load becomes '1' then only all 4 dff stores data into it and when load is '0' i need to shift it serially..so i want to do port mapping(1st) when load is '1' and if load is '0' then other port mapping(2nd)..
also if you have another idea plz tell me but i need to do it with structural modeling only..thanks in advance
 

Re: Can i do conditional port mapping in VHDL??

you cannot do conditional port maping, a port mapping is like the pins on a chip. So disconnecting them would be impossible while the design is running.

How about posting some trial code, and we'll try and fix it.
 

Re: Can i do conditional port mapping in VHDL??

TrickyDicky said:
you cannot do conditional port maping, a port mapping is like the pins on a chip. So disconnecting them would be impossible while the design is running.

How about posting some trial code, and we'll try and fix it.
Click to expand... 

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity piso_struct is
    Port ( din : in  STD_LOGIC_VECTOR (3 downto 0);
           dout : out  STD_LOGIC;
           clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           load : in  STD_LOGIC);
end piso_struct;
 
architecture Behavioral of piso_struct is
 
COMPONENT dff
    PORT(
        din : IN std_logic;
        load : IN std_logic;
        reset : IN std_logic;
        clk : IN std_logic;          
        dout : OUT std_logic
        );
    END COMPONENT;
    
signal temp:std_logic_vector(3 downto 0):=X"0";
 
begin
 
if (load='1') generate
 
Inst_dff1: dff PORT MAP(
        din => din(0),
        load => load,
        reset => reset,
        dout => temp(0),
        clk => clk
    );
Inst_dff2: dff PORT MAP(
        din => din(1),
        load => load,
        reset => reset,
        dout => temp(1),
        clk => clk
    );
Inst_dff3: dff PORT MAP(
        din => din(2),
        load => load,
        reset => reset,
        dout => temp(2),
        clk => clk
    );
Inst_dff4: dff PORT MAP(
        din => din(3),
        load => load,
        reset => reset,
        dout => temp(3),
        clk => clk
    );  
    
end generate;
    
if (load='0') generate
 
nst_dff1: dff PORT MAP(
        din => temp(0),
        load => load,
        reset => reset,
        dout => temp(1),
        clk => clk
    );
Inst_dff2: dff PORT MAP(
        din => temp(1),
        load => load,
        reset => reset,
        dout => temp(2),
        clk => clk
    );
Inst_dff3: dff PORT MAP(
        din => temp(2),
        load => load,
        reset => reset,
        dout => temp(3),
        clk => clk
    );
    
end generate;
    
dout<= temp(3);
 
end Behavioral;


errors are..

 
Last edited by a moderator:

Re: Can i do conditional port mapping in VHDL??

Presumed you want to write pure structural code, connect multiplexers between the dff din and dout ports.
 
Re: Can i do conditional port mapping in VHDL??

Generates require a label:

my_label_gen : if X = something generate..

But the other issure is you cannot use a signal in a generate - it must be a constant (so only a constant or generic can be used).

You need to use a mux like FvM suggested.
 
Re: Can i do conditional port mapping in VHDL??

TrickyDicky said:
Generates require a label:

my_label_gen : if X = something generate..

But the other issure is you cannot use a signal in a generate - it must be a constant (so only a constant or generic can be used).

You need to use a mux like FvM suggested.
Click to expand...

thanks use of mux solved my problem..

but buddy i have used signal in generate statement for another program and it worked fine..

see this code. its for carry look ahead adder..
Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity carry_look_ahead is
    Port ( a : in  STD_LOGIC_VECTOR (7 downto 0);
           b : in  STD_LOGIC_VECTOR (7 downto 0);
			  s : out  STD_LOGIC_VECTOR (7 downto 0);
           cin : in  STD_LOGIC;
           cout : out  STD_LOGIC);
end carry_look_ahead;
architecture Behavioral of carry_look_ahead is
signal p,g,c: STD_LOGIC_VECTOR (8 downto 0);
begin
c(0) <= cin;
loop_init: for i in 0 to 7 generate
p(i) <= a(i) xor b(i);
g(i) <= a(i) and b(i);

s(i) <= p(i) xor c(i);
c(i+1) <= g(i) or (p(i) and c(i));
end  generate loop_init;
cout <= c(8); 
end Behavioral;
 
Last edited:

Re: Can i do conditional port mapping in VHDL??

The generate parameter isn't a signal. It's a loop index evaluated at compile time, generating parallel logic instances.
 

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