ehsan_iut
Junior Member level 1
Hi folks,
Is it possible to access to the signals of lower level modules from the top module? I think it would be very useful in writing test benches. Or we should bring those signals to the test bench by means of ports? Tnx.
Is it possible to access to the signals of lower level modules from the top module? I think it would be very useful in writing test benches. Or we should bring those signals to the test bench by means of ports? Tnx.