zhangljz
Member level 5
- Joined
- Oct 19, 2013
- Messages
- 81
- Helped
- 1
- Reputation
- 2
- Reaction score
- 1
- Trophy points
- 8
- Activity points
- 648
Is it okey to use a counter as a pll integer N divier ?
Hello,
I am designing a PLL with low output frequency (~350MHz, reference frequency: 10MHz). I want to have a divider ratio from 1 ~ 63.
Because the frequency is low, and divider ratio is not very high, is it ok to just use a synchronous counter synthesized by verilog to work as a divider, instead of using swallow method. Also I am not familiar with the swallow counter.
Any advice?
Thank you
Hello,
I am designing a PLL with low output frequency (~350MHz, reference frequency: 10MHz). I want to have a divider ratio from 1 ~ 63.
Because the frequency is low, and divider ratio is not very high, is it ok to just use a synchronous counter synthesized by verilog to work as a divider, instead of using swallow method. Also I am not familiar with the swallow counter.
Any advice?
Thank you