Is it legal to use always block inside verilog "generate for" ?

mr_vasanth · Mar 5, 2014

Code Verilog - [expand]
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parameter SIZE = 3;
 
reg [31:0] reg_name [0:(SIZE-1)];
 
generate 
    for (i=0; i<SIZE; i=i+1)
    begin : MULTI_REG
      always @(posedge clk_i)
        reg_name[i] <= data_in;
    end
 endgenerate

is it legal to have always block inside a "generate for" statement as shown above ? is this synthesizable ? what will be the synthesis result ?

Don't mind about functionality of this circuit !!

dave_59 · Mar 5, 2014

Yes. Anything listed in the BNF under module_or_generate_item or module_common_item can put put inside a generate block. You will need a declaration genvar i;. The loop will be unrolled and i will be replaced by the appropriate constant. Synthesis will proceed just as if you had manually written each individual always block.

Is it legal to use always block inside verilog "generate for" ?

mr_vasanth

Member level 5

dave_59

Advanced Member level 3

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Code Verilog - [expand]
1 2 3 4 5 6 7 8 9 10 11	parameter SIZE = 3; reg [31:0] reg_name [0:(SIZE-1)]; generate for (i=0; i<SIZE; i=i+1) begin : MULTI_REG always @(posedge clk_i) reg_name[i] <= data_in; end endgenerate

Is it legal to use always block inside verilog "generate for" ?

mr_vasanth

Member level 5

dave_59

Advanced Member level 3

Similar threads

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