Is it good to do verification using verilog pli?

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zhangpengyu

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what's verilog pli

Hi
guys!

Is it good to do verification using verilog pli?Does vcs support it?



zhpy
 

Re: what's verilog pli

Verilog PLI( Programming Language Interface) is a mechanism to invoke C or C++ functions from Verilog code.

For Mixed-Langulage Co-Simulation
 
Re: what's verilog pli

VCS support it , in different form of function call
 

Re: what's verilog pli

zhangpengyu said:
Hi
guys!

Is it good to do verification using verilog pli?Does vcs support it?



zhpy
Click to expand...

Hi zhangpengyu:

Pli is very useful because the verilog is weak of some aspect (for

example: file process ability) . You can use verilog PLI to do this work.

Luckly, the verilog-2001 have better ability, you can do something with

the system task of verilog.

Mainstream digital simulator support the use of PLI.

wang1
 

Re: what's verilog pli

hi,
Many simulation tools support this. VCS, NC-Verilog etc.

But I think when you do verification, Perl is very good language for dealing the result files. And shell will help you build the automatic test enviornment.

For my opinion, PLI is more difficult than perl and shell.
 

Re: what's verilog pli

A very good book about PLI:

The Verilog PLI Handbook
by Stuart Sutherland 2/e
Kluwer Academic Publisherd

for your reference( I have't find eBook , sorry)
 

what's verilog pli

of course. vcs support it.you can see cadence document.
 

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