korea fabless company
I suppose it is all relative:
It costs about 2-4 Billion to build a Fab and about 4 million a month to run it (including salaries, consumables etc). So you need to make a lot of profit to keep a Fab going.
So fabless must be easy right?
To be fabless, 1st you need a design tool set that is compatible with the Foundries (Cadence, Synopsis etc) The license and maintenance costs of these are substantial certainly above $400,000.
Then you need to make sure your design idea can run on a standard Foundry process and if it can, then it is probably not a brilliant cash cow since it will be digital or fairly low frequency mixed mode which someone with more money will beat you at eventually if it is such a good idea.
If you want to go into complex RFBiCMOS or RFCMOS where there is less competition, then standard Foundry models may not be good enough to guarantee 1st pass design success and you may need a design re-spin or two for each new product idea. This will cost you (more in a minute).
Since you cannot fully rely on the foundry models, then you need your own RF test set up to optimise your design to their process. Add on another $400K for this. You need the skills to run it and it takes a lot of time! So you need to employ an RF parameter extraction guru who can run Agilents IC-CAP software and hardware.
Now you need to get your design into a layout and onto GDS II. In mixed mode and RF, you are likely to encounter Design Rule Violations that the Foundry will ask you to fix. So you need to hire (or be) a layout guru.
OK now your ready to go. Well the smart choice would be to get onto the Foundry MPW run where you share mask space for prototypes with other customers on the same technology. It means only a few devices for you to test and know you design is ready for production. This typically costs $20,000+ at 90nm and 130nm.
If you design doesn't work you may need to wait 3 months for the next MPW run and there is no guarantee there will be one (if not enough customers want space it)
OK now your design works and ready for production. Well now you have to buy the reticle set (masks for the lithography process). A set of masks for one design will cost you about $55K for 0.25um through $300K for 0.13um and upto $1M for 65nm.
This is for each device you run. And if the design needs to be changed or tweeked, it will cost you some percentage of this to replace the masks.
Now you have to pay for the wafers that are run. Well, if you are a big guy and want 30% of the Foundry Fab capacity, they will kiss your feet with their rock bottom prices.
Otherwise they will screw you. So expect to pay $400 per wafer at 0.18um, $6-700 for 0.13um and do not even ask about 65nm!
Also, if you do not buy sufficient quantity over a sufficient time (say like at least 200 wafers per month) they will probably not want your business, which brings in another point.......
You are never guaranteed Foundry capacity unless you are big and trusted. So if ST Micro want extra 200 wafers per month from TSMC guess who they are going to boot out? And now what do you do? Sulk of course but then go elsewhere ?
Well if it is an easy digital part with rock solid design insensitivities you'll find somewhere. If it is a complex mixed signal RF monster, it just will not work anywhere else because you had to tweek your design and buy all that expensive agilent equipment and hire the RF guru.
Now the easiest way to vent your frustration at this point is the get the expensive RF guru you just hired and kick the living day lights out of him/her. It will not help the situation, but you will feel a wee bit better.
Now lets say you are now getting your supply of finished wafers from somewhere. You have to test them. This is done at a Test Foundry thingy. The Wafer Fab Foundry does not do this. So you have to hire STATS or the likes to test your wafers.
Now you need to write the test program, so you have to hire a test guru who is familiar with the test equipment the particular test contractor uses and they are not all the same.
You also have to get the wafers sliced up bonded and assembled. This will cost anywhere from $0.40 - $4.00 per chip. In most cases the Assembly Contractor will do test as well but RF testing is very difficult and you can lose 30% yield because the prober was not set up correctly on monday nightshift because the operator had an almighty row with her partner before leaving for work. And it rained too !
Now you have at least 200 wafers per month with probably 1000 to 12000 chips per wafer depending on their size (the bigger, the more expensive the packaging). More money and we have not sold anything yet !!
Well its 2 years later and the chips are selling well, the RF guru has recovered from his injuries, the Test guy is surfing the web behind your back and the layout guy is busy working because they are really sad that way. All of a sudden your yield drops at the assembly house. Now your losing 50% of every chip to some failure.
You can go back to the Foundry claiming they have a problem that is costing you money and some grief from your customers.
The Foundry will listen symapthetically and then say ........
It must be an assembly of a design fault because no other customer is having a problem on that technology.
At this point you will notice they are reading this off a rather worn laminated card they are trying to hide, because that is what the said to the other customer yesterday.
But you are a small fish and, the motto of every Foundry is :
"the Customer is always first ......... to get the lie about it being a problem unique to their design....."
Now you have to hire a Failure Analysis Expert (nand if you think layout guys are sad .....) and you have to buy him/her a reverse engineering laboratory with electron microscopes, wet chemical etch benches, plasma etchers..... realy cool toys by the way;
This will cost about $3-4M and you have ended up with a mini Fab that goes backwards !!! So much for being a Fabless company.
But life would be so dull if it were easy .................;