is it difficult for a vcxo to lock to a reference?

[ddt694]

vcxo loop filter

I had designed a pll, the reference is a 10MHz ocxo, the FPD is analog device's ADF4001 pll chip, the vcxo(not a vco) output frequency is 70MHz, and the sensitivity is very low(5Hz/v).


The loop is very difficult to in locked, and the loop parameters are very surprising-- the feedback resistor is 12000000000ohm, the feedback capcitor is 14.1fF(what is fF?).

i suppose this is because the filter have to be high gain to compensate the low sensitivity of the vcxo.

i want to know, if the vcxo Pll is really difficult to be in locked? and what is the implementable method?

may be i should use a all digital pll, say, all the FPD is realized in a CPU or a FPGA, and the control voltage is generated by a DAC, the output of the DAC is tied to the control pin of the VCXO?

regard
ddt694

 

[biff44]

locking vcxo reference

Should make no difference. The vco tuning constant is very low, but you are only dividing the VCO by 7, so the control loop open loop gain is reasonable, just a little larger than you are used to. Try using a wider control loop bandwidth. Try using big capacitors in the loop filter (10 uF, etc) and lowering the resistance values. If you are using an op amp, maybe it is getting stuck on a supply rail. You might have to limit its voltage output range (zener diodes in the feedback arm), or some sort of sweep lock circuit. The XTAL oscillator tuning response might have a large time delay, causing some loop instability--so make sure you have lots of phase and gain margin.

 

[ddt694]

adf4001

thanks,biff44

if i can say to use a vcxo in a pll, i must following these rules:

(1) the compare frequency should be as high as possible
.
(2) the loop bandwidth should be as wide as possible.

(3) setting the phase margin much above 45 degree, for example 90 degree.

are the rules right?

 

[toonafishy]

control vcxo with a dac

I would think the loop gain is very low due to the low tuning sensitivity of the VCXO. The VCO probably has a much higher gain (MHz/Volt) than the VCXO (kHz/Volt).

 

[biff44]

vcxo open loop

Sorry, I misread your orignal post. I thought you were trying to lock a 70 VCXO to a 10 xtal osc. You VCO probably has a relatively high tuning constant.

To get a 1 MHz bandwidth, forget the bigger capacitor comment.

Just make sure your op amp, loop reference spur filter, and vco tuning ports have lots of bandwidth (very little phase shift at 1 MHz), or you will have an unstable loop at 1 MHz.

 

[echo47]

vco vcxo difference

12000000000 ohm = 1.2e10 ohm.
14.1 fF (femto farad) = 1.41e-14 farad.
Certainly not very practical values, but multiply them together and you get an RC time constant of 169 microseconds. You could get the same time constant by using a 12K resistor and 14.1 nF capacitor.

Your original post is a bit unclear. What type of oscillator are you trying to lock to what type reference?

Once upon a time I built a PLL that locked a 10MHz voltage controlled OCXO to a GPS reference. The loop time constant was around an hour.

 

[ddt694]

vcxo vs vco

I would think the loop gain is very low due to the low tuning sensitivity of the VCXO. The VCO probably has a much higher gain (MHz/Volt) than the VCXO (kHz/Volt).

hi, toonafishy, thanks for your help. if i use a vco instead of a vcxo, the loop is of course easy to be in locked, but i have to use a vcxo for some other reasons.

Added after 6 minutes:

Sorry, I misread your orignal post. I thought you were trying to lock a 70 VCXO to a 10 xtal osc. You VCO probably has a relatively high tuning constant.

To get a 1 MHz bandwidth, forget the bigger capacitor comment.

Just make sure your op amp, loop reference spur filter, and vco tuning ports have lots of bandwidth (very little phase shift at 1 MHz), or you will have an unstable loop at 1 MHz.

hi,biff44
sorry to trouble you so much. yes, i am trying to lock a 70MHz vcxo to a 10MHz reference(ocxo).

 

[biff44]

using vcxo

No need to be sorry, there is often a language barrier.

Just to clarify:

You are trying to lock a 70 MHz VCXO to a 10 MHz reference.

I would try to do so in a small loop bandwidth at first. Pick a resonable control loop bandwidth, say 1 KHz, and design components for it. Odds are it will lock right up. You will find that you probably do need large capacitors in the loop filter (5 uF or bigger). If you try to use a small capacitor and a large resistor, you will end up with too much thermal noise in your loop filter.

Do realize that the VCXO will have a limited frequency tune range, so make sure that the reference is really at 10 MHz, and the VCXO is really starting at 70 MHz.

Once it is working in a narrow loop bw, you can try to make it a bigger bandwidth. But, you will not be able to work beyond the 3dB bandwidth of the tuning port. You should determine the tuning port's 3 dB bandwidth before by experiment.