Is it a tutorial talking about bottleneck of pipelined ADC?

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barry0107

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Hi,

I am looking for a tutorial or any document about the bottleneck of pipeline ADC. For example, normally the clock jitter is hard to be better than 1p RMS sec. Therefore, we know it is not easy to create a pipeline ADC better than this resolution. Is there any teaching lecture or tutorial talking about the bottleneck of pipeline ADC based on the popular technology NOW? Thanks a lot.


BR,
Barry
 

Re: Is it a tutorial talking about bottleneck of pipelined A

Clock jitter is not a bottleneck of pipeline ADCs or any ADC, for what matters.
If you want to read documents on ADC design, try:
https://iadc.ca/Pipeline_ADC_tutorial.htm
**broken link removed**
or L. Sumanen and M. Waltari PhD dissertations, for example.
 

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