is Development board like DEO-nano appropriate for sequencer?

[xeloradio]

I am considering replacing a lot of TTL logic and an Arduino etc,
and expanding the functionality of a project.
I have some questions about using the DEO FPGA development board
(small Altera Cyclone) or similar:
A) I need to run it strictly on 5V battery after programming because of
EMI from USB
B) I need to interface all IO to 5V signals
( and from 5 V some to swing + and -)
C) Is it possible to use a 1 MHz clock instead of 50 MhZ?
(maybe by PLL, but I need to synch to the 60 Hz power line)
D) Long ago I programmed using VHDL on Altera Stratix
Maybe I need to relearn this for
i) very long chains of shift registers running at e.g. 20 Hz
ii) clocked one-shots,
iii) many delays and pulse widths (e.g. 20 or 30) now done a
combination of 555 timers
and clock-
or is this best done with included C language?

 

[ads-ee]

I am considering replacing a lot of TTL logic and an Arduino etc,
and expanding the functionality of a project.
I have some questions about using the DEO FPGA development board
(small Altera Cyclone) or similar:
A) I need to run it strictly on 5V battery after programming because of
EMI from USB

Cyclone IV (on DE0) uses 1.2V (core), 3.3V (I/O), and for the PLL 2.5V, and a cleaner 1.2V

B) I need to interface all IO to 5V signals
( and from 5 V some to swing + and -)

The Cyclone IV doesn't have 5V tolerant I/O from what I can see from the datasheet. Nor can it interface directly with +/- 5V (I don't know of any FPGA that does that. You might require level shifters to interface the part with 5V.
You should consider looking at Microsemi parts, from a power standpoint they are much lower than SRAM FPGAs from Xilinx/Intel(Altera). If you can find an older generation part (doubtful) they had 5V tolerant I/O, the newer parts like Igloo2, Polarfire, and Smartfusion2 all are 3.3V parts. The benefits of using a flashed based part is it is instantly on after power-on like your SSI circuit and it's very low power so battery operation benefits significantly.

C) Is it possible to use a 1 MHz clock instead of 50 MhZ?
(maybe by PLL, but I need to synch to the 60 Hz power line)

Sure you can use a 1 MHz clock but the PLL might not be able to output such a low frequency clock and it definitely won't produce a 60 Hz output or be able to sync to a 60 Hz clock source.

D) Long ago I programmed using VHDL on Altera Stratix
Maybe I need to relearn this for
i) very long chains of shift registers running at e.g. 20 Hz
ii) clocked one-shots,
iii) many delays and pulse widths (e.g. 20 or 30) now done a
combination of 555 timers
and clock-
or is this best done with included C language?

VHDL isn't that much different from a long time ago to now, new features sure and some simplifications to how you can write code, but what you knew before should compile just fine now.
What I think you need to concentrate on is not writing code that implements exactly what you had before with long shift registers, one-shots, and a bunch of delay timers and look at the problem from what it is supposed to do and then come up with a design that is both simpler and easier to implement in VHDL, than just translating some SSI TTL circuit directly in VHDL.

 

[xeloradio]

Thanks.
Overall this looks promising. Also, I forgot that I am already using a dozen or so optical isolators, ACPL-021L, and it turns out that these can be driven from 3.3 V and will drive 5 V CMOS, etc.