Is +/- 1n PLL jitter performance good?

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silicon

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PLL jitter

I have designed a PLL and tape-out.
The reference clock is 80KHz, and the feedback divider ration is 256.
Loop filter is built in chip.
The peak-to-peak cycle-to-cycle jitter is about +/-1n.
Is the jitter performance resonable?
 

Re: PLL jitter

You will need to make phase noise measurements to get a good idea of the signal accuracy. And that's equivalent to jitter.
 

Re: PLL jitter

silicon said:
I have designed a PLL and tape-out.
The reference clock is 80KHz, and the feedback divider ration is 256.
Loop filter is built in chip.
The peak-to-peak cycle-to-cycle jitter is about +/-1n.
Is the jitter performance resonable?
Click to expand...


+/-1ns jitter is real chip measurement.
 

PLL jitter

your output frequency is 2MHZ,the jitter is +/-1ns ,if your measurement is right and the result is accurate,its reasonable.
 

Re: PLL jitter

jodenma said:
your output frequency is 2MHZ,the jitter is +/-1ns ,if your measurement is right and the result is accurate,its reasonable.
Click to expand...

Sorry.. The output frequency is 20MHz.. period is 50ns
 

PLL jitter

Yes,It is reasonable, it just 2% jitter of your output clock.
 

Re: PLL jitter

The jitter requirements depend on the use of the clock.
If it is used as a clock for a full digital system, it is fine but if it is used as a clock to sample a signal with a high dynamic range ADC, the phase noise of the clock effect will be equivalent to sampling the input signals with an ideal clock, but all the input signals will have phase noise equal to the clock original phase noise, and that can corrupt the input signal completely, depending on the application.
 

Re: PLL jitter

Hi,
The jitter spec depends on your applications.
Due to your output 20MHz, +/-1ns jitters just only +/-2%.
I think it's good enough!
 

Re: PLL jitter

pleas note the peak-to-peak cycle-to-cycle jitter is not as good as a jitter accumulation measurement.
 

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