you could always try simulating it....you cant simulate the ir2110, but you can simulate eg the LTC4440 in LTspice which is a similar bootstrap operation.
Also, if youre layout is bad you get other problems too...for example the VS pin can ring below ground, and you really need a suitable ultra fast HV diode from VS to GND.......cathode to VS.
also, it is standard to add protection zeners on the gate-source of each fet.
Also a series say 5r1 resistor in series with the bootstrap diode to limit inrush.
Which differential probe are you using also? You need to scope the upper fet GS and the bootstrap cap voltage....if you are doing that without diff probe then you are putting gnd of probe onto a node with high dv/dt, which cause you problems.....differential probe is needed.