IR2110 LTspice simulation weird behaviour

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cdez

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Hello,


I simulated an IR2110 on LTSpice on a 1k load with only high side drive.



PWM config :
rise time = 1.75u
fall time = 1.75u
on time = 40u
period time = 50u

(it's 20khz with high duty cycle)

Weird results with voltage dropping on gate:



If I reduce the bootstrap capacitor or the load, it works fine, looks like bootstrap charging or discharging from the load ?

Is that normal ?
 

Do you mean I need to send the inverse pwm to the low side ?
 

This setup doesn't work. Without activating the low side driver complementary to high side, the bootstrap capacitor can't be recharged.

- - - Updated - - -

Something like this. The gate RD circuits will hopefully achieve suffcient dead time and prevent cross conduction.
 


will it work if I do like this:

PWM1_Set_Duty(X); // high side
PWM2_Set_Duty(255-X); // low side
Click to expand...
This won't necessarily end up with complementary PWM signals. Why don't you read the PIC18 user manuals, they are discussing different PWM operation modi in detail.

What I meant is that with your RD circuit, a simple inverter can already give sufficient dead time, although programmable dead time is basically preferable. But involves the risk of creating a bridge short with programming faults.
 

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