abcyin
Full Member level 4
Hi, all,
I am trying to design a circuit to compensate the IQ phase imbalance, which could be caused by layout mismatch, process and so on. Documents show that delay cell could be used to do such a thing, but how to realize the phase calibration automatically? could anyone give me some ideas? or papers are also welcome.
Thanks in advance,
abcyin
I am trying to design a circuit to compensate the IQ phase imbalance, which could be caused by layout mismatch, process and so on. Documents show that delay cell could be used to do such a thing, but how to realize the phase calibration automatically? could anyone give me some ideas? or papers are also welcome.
Thanks in advance,
abcyin