IP core generator problems when parameters of a core are changed

[osbourne]

When I instantiate an ip core (e.g. a DCM), there's no problem. But when I change parameters of this core, the design synthesizes no more and error messages appear.
What is the problem ?

 

[Renjith]

ip core cosinus

mention whatz the error?
when u changed the parameters, whether the coregen gave any warning?

 

[osbourne]

dcm core generator

I use the sin/cos look up table ip core. It has the name <carrier_gen> in my design. The width of the theta input is initially 4 and the design works. When I change the width to e.g. 6, the following warnings appear:

Regenerating IP...
WARNING:sim:89 - A core named <carrier_gen> already exists in the output directory. Output products for this core may be overwritten.
WARNING:coreutil:266 - Could not remove outfile.

I also changed the width in signals of the rest of the design to 6 to match the new
ip core spec.

Then, when I try to synthesize the new design I get the following error message:

ERROR:Xst:2091 - "d:/xilinx/pd/DPD.vhd" line 79: Different types for port <THETA> on entity and component for <carrier_gen>.

THETA in entity and component do have the same type !! So I don't understand this error ? Can somebody help ?

 

[Renjith]

IP Core generator

Hi,
i generated a model using the sine/cos lut ip core.
went with the same way u mentioned.
intially giving a theta width of 4 and then regenerating it with 6. but i have not met with any error.

now... have u generated the model by calling coregen from the ISE environment using " create new source".
or did u activated coregen intially and then included ur vhdl model using "add an existing file"

check out ur "*.out" file also and c whether the changes are updated.

or just give the .xco file for ur model,
so that i can enter the same parameters to checkout ur prblm.

 

[osbourne]

Re: IP Core generator

Hi,

please find attached a small vhdl model using a DCM and the sin/cos look up table to
generate a sine and a cosine function.

THETA width is now 4. If you double click on "carrier_gen" in the sources in project window, the corresponding core generator window opens. Please change THETA width to e.g. 6 and click generate. Now "carrier_gen" should be updated. Try to synthesize the model again and you will find the mentioned warnigs/error.

Thanks for helping me !