IO cell and power decoupling

[bluestatic]

io cell

HI, all
I'm designning an anlog IO cell, after layout, there are still some spare space left within the IO cell. I want to put some power to groud decoupling capacitor into these spare space (mos cap, most probably). Do you see any problem with it, I mean, in terms of ESD and some other relative issue. thanks.

 

[alok_ky]

Adding the decoupling cap at the spare space is not a problem.
Just make sure that the parasitic resistance associated with the decoupling cap connection to pwn and gnd is minimum.

 

[sunking]

it is OK.
please pay attention to the space of design rule

 

[SkyHigh]

bluestatic,

You are dealing with analog IC, not digital IC for high-speed switching, thus adding additional de-caps helps little. But you can add them anyway to provide a clean analog power and ground. For me, I will expand my well (horizontally) and add more contacts to minimise latch-up and minimise threshold variation (in short-channel MOS).

 

[jiangwp]

I think the loading for input signal is incresed when the decoupling capacitor is added for the signal pad with exception to the power supply.

In the meanwhile, generally, the input capacitor of cmos circuit is large, if the addtional capacitor is used, the ESD level will be decrese with increased capacitor.
The reason is below,
little variation in input, and due to the large input capacitor, the acculated charge is larger. So, the discharge time is increased, the propability for damage of ESD is increased.

If the addtional capacitor is used for output pad, they will increase the loadding for the output buffer. So the larger power dissaption will be needed.

 

[SkyHigh]

We are talking about de-cap added between Power and Gnd, not Input.

BTW, ESD is resolved by clipping diodes and series I/O resistance of the I/O line. Adding de-cap to the input is building LPF in the input, thus limiting the bandwidth of the input signal. I won't advise add de-caps to input.