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In my application, your first guess - with the

downstream C and some "sharpening back up"

you have a current-controlled delay stage

(one-sided - the HL is not strongly affected

except by the drive-strength balance moving

effective inverter DC threshold, the LH can

go from "2 Rds in series" to "open").

I use a "sniffer" bias circuit on a pad, where the

user can hang a set-resistor, to develop user

settable nonoverlap timing in a gate driver.

Force a voltage, take the current, bounce it

back onto the inverter Vdd, badda-bing.