Inverter interharmonic in simulation? Is this typical? Unstable at ~50ms mark?

[pjcircle1]

I am trying to learn about inverter design etc. and am simulating a basic sinusoidal pwm controlled, 3ph inverter on PSIM, the load has a PF~0.9 and the switches are ideal in the inverter. I had a few questions about these waveforms I am getting.

1. In the FFT why am I spiking at ~80Hz when my carrier freq is 900Hz and modulating frequency is 60Hz? This is called an interharmonic correct? It seems to only be in the current switching waveform and the load waveforms not the voltage switching waveforms? There also seems to be a spike ~104hz but I think that is filtered out effectively in the output.
2. What is going on before the load waveforms reach steady state? Is that big dip ~50ms from the 80Hz interharmonic?
3. Any other pointers of what to look out for when modeling these things would be appreciated! I am going to try overmodulating and using third harmonic injection after I sort out what is going on with this basic sim and eventually move on to SVM. Really trying to nail out some basics first.

 

[FvM]

The waveforms look like transient solution, e.g. startup. Impossible to recognize if it reaches steady state at second half of simulation. FFT of non steady state is almost useless.

 

[pjcircle1]

The waveforms look like transient solution, e.g. startup. Impossible to recognize if it reaches steady state at second half of simulation. FFT of non steady state is almost useless.

I reran the FFT and a longer simulation. It visibly looks like steady state now, unsure if theres a way to validate that in this simulator. The interharmonic did disappear and the FFT definitely looks more like a would expect. That 104Hz spike is still in the switch current waveform though. Unsure what that is from.

 

[FvM]

Not clear what makes the difference between FFT traces, some have the "104 Hz" line, others don't. But I'm sure you can find the reason if you look deeper I to the signal processing.

 

[BradtheRad]

Your output stage has the LC arranged as a 2nd order low-pass filter. 80 or 90 or 100 Hz is a reasonable rolloff frequency to remove everything above 60 Hz. It's also possible to cause a kind of ringing or oscillating at that frequency especially if the load is high impedance. It's similar to a caution stated by amplifier builders, that is, always connect a load when operating this type of filter. Your schematic has resistive loads attached although the L:C ratio should be customized to the load. And 3-phase delta may raise its own complications.

 

[pjcircle1]

Your output stage has the LC arranged as a 2nd order low-pass filter. 80 or 90 or 100 Hz is a reasonable rolloff frequency to remove everything above 60 Hz. It's also possible to cause a kind of ringing or oscillating at that frequency especially if the load is high impedance. It's similar to a caution stated by amplifier builders, that is, always connect a load when operating this type of filter. Your schematic has resistive loads attached although the L:C ratio should be customized to the load. And 3-phase delta may raise its own complications.

Thank you Brad, i've been collecting some information on this and the agenda today will be.

1. To actually get the .9 PF I need the complex impedance on the load, I was calculating the PF using the resistor and the filter.

2. Actually have a goal cut-off frequency, I was just trying to match to a PF for the RLC network. Someone recommended a pi filter as that is typically used in inverters I might play around with that too.

3. Ground the capacitors.

 

[mtwieg]

I'm quite sure that spike is at 120Hz, not 104Hz, which would make much more sense.