Inverter Chain Synthesis Problem

Status
Not open for further replies.
D

davyzhu

Advanced Member level 1
Joined
May 23, 2004
Messages
494
Helped
5
Reputation
10
Reaction score
2
Trophy points
1,298
Location
oriental
Activity points
4,436
inverter chain synthesis

Hi,

I work on Xilinx ISE, and my synthesis tool is XST and synplify.
I use verilog to write a Inverter Chain (delay ) like out = ~(~(~(~...in)).
But the circuit be synthesised cancel all the invorter.

How to synthesis out all the inverter chain I want?

Any suggestions will be appreciated!
Best regards,
Davy
 

You need to declare individual wires for each signal (not just a boolean expression with lots of ~ operators), and then use the KEEP constraint to prevent XST from optimizing them away.

Code: 
module top (in, out);
  input             in;
  wire        [7:0] delay;  // synthesis attribute KEEP delay TRUE
  output            out;

  assign delay = ~{delay[6:0],in};
  assign out = delay[7];
endmodule
Why do you want such a thing? Delays are usually something to avoid.
 

    D

    davyzhu

    Points: 2
    Helpful Answer Positive Rating
Hi echo47,

Thank you

My friend want to generate a random data generator. And he need a delay loop.

Do you think what's the best way to get delay in FPGA (delay smaller than one clock period)?

Best regards,
Davy
 

I'm curious -- how will a delay help you build a random data generator?

Delays are usually bad things. Try modifying the design to eliminate the need for delays.

If you really need a half-clock delay, or a third-clock delay, or something like that, then I would consider using a frequency multiplier (such as Xilinx DCM) to increase the clock frequency, and then use it to clock a small shift register that delays the signal.
 

Hi,

Ah, I read a applicatoin note about digital PLL from Xilinx. They use MUXCY (fast carry chain) to build a more precise comb delay in FPGA.

As for random data generator, I don't know how to generate it in digital way. Any my friend said it's a secret :-(. Do you have any idea?



Best regards,
Davy
 

You can't built a true random number generator digitally.

You can build a pseudo-random number generator digitally. For example, a simple linear feedback shift register (LFSR) outputs a pseudo-random bit stream:


There are countless other pseudo-random number generators of varying quality. Search Google.
 

    D

    davyzhu

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…