Inverter and slewing

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parkpika

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Do CMOS inverters slew when presented with a sine wave input around Vdd/2?

What causes slewing in CMOS inverter? Does it slew because the gain is really high?
 

Slewing is how quickly a circuit can change its output voltage. Output capacitance can slow down slewing.
At Vdd/2 the gain of a Cmos inverter depends on its supply voltage. The gain is reduced at higher voltages because the two Mosfets load each other.
I showed a graph about it in your other thread so why did you make this new thread instead of continuing the other thread?
 

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