intuitively, in pll,why loop bandwidth <=1/10 reference f

[freewing]

I know this can be derived by math. Can this be explained in an intuitive way?

 

[rfsystem]

Re: intuitively, in pll,why loop bandwidth <=1/10 referen

Why not 13/127?

Read

 

[khouly]

Re: intuitively, in pll,why loop bandwidth <=1/10 referen

when u azalyze the PLL as a feedback system we use S domain , which mean that u assume that the PLL is a countinuse time system
but actually PLL is sampled system cause it contain a digital part PFD

so we need the bandwidth of the loop to be at leat 1/10 of the refernce frequency to insure that any variation id the loop condition will be fast . and the loop sense that the refernece is continuse

this is called continuse time approximation of the PLL

if u want to design a PLL with loop bandwidth greater 1/10 of refernece frequency
u will need Z domain techniqucs to analyze the PLL

wish this help

khouly

 

[eng_Semi]

Re: intuitively, in pll,why loop bandwidth <=1/10 referen

This value is the near the optimum value to have a fast loop and high spurs attenuation.

 

[rfsystem]

Re: intuitively, in pll,why loop bandwidth <=1/10 referen

Could you specifiy the condition for spur and speed which lead to the number 1/10? Is that affected by the order and relative pole positions.

It is easier to state that there is

1. A modelling issue with a s-description of a time discrete and value continuous system.

2. There is trade between locking time and rejection of spurious signals resulting from up to now not mention second order imperfections.