Intuitive explanation of using delay line for switched capacitor simulation

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Hi all,

I've looked through some of the questions and seen some references sourced here. But haven't found a satisfactory intuitive explanation.

I'd like to simulate some AC switched capacitor systems in ltspice, without having spectre/cadence access for pss analysis.

I've seen examples that use a delay line and negative resistance (storistor) to emulate a delay (z^-1/2). And I can build a simulation giving a sinc ac response as I might expect.
In Baker's excellent text on advanced circuits, he describes a comb filter without any negative resistance.

I get that the delay line is just a z^-1 shift of one period in time here, but don't get the negative resistor contribution or how the system translates to transfer function equations or direct analog circuit implementation (esp for larger systems).

I have some references (Allen Hollberg, Sansen, etc). But none really elaborate in such a way I can get an intuitive understanding.

I would really like to get my hands on SWITCAP as every reference seems to utilize it outside of Spectre. But I can't find it anywhere.

Any help is appreciated.

edit. I've attached a (translated) example from VLSI Analog Filters: Active RC, OTA-C, and SC , Mohan.
They reference out of print Laker texts, but never really elaborate much on the negative resistance or how these translate to actual
equations (transfer function, 3db etc). I tried to use f3db = 1/2pi10k*1n and similar, but my results are way off from the output 3db.
I can also try f3db = 1/(2*pi*(10k//50)*1n) = 3.2MHz. Brings me closer, but not quite. Other variations trying to calculate net resistance with tline don't seem to come out either.
 
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It would be interesting to see the the SC circuit you are trying to emulate. I don't see a relation of the simulation circuit to negative resistance, it implements a classical inverting integrator along with the comb filter.
 

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FvM said:
It would be interesting to see the the SC circuit you are trying to emulate. I don't see a relation of the simulation circuit to negative resistance, it implements a classical inverting integrator along with the comb filter.
Click to expand...
Thanks for your response. From my limited time here, you seem to be pretty experienced in this area.
Ref. is IEEE transactions CAS-30 Nelin B.D. 83. I think I've seen you reference this paper in another post. It is very possible I did not translate correctly to LTSPICE. I don't have access to that paper or journal, unfortunately. They call it a sample and hold in the book and the response seems to be what I would expect from that (sinc rolloff). Baker's text shows a continuous comb filter without the negative resistor that is similar (no sinc rolloff, it is just repeating comb).

I would be grateful to see an example with an explanation of TF calculations for a circuit like below (f3db of sampled system etc). I can't find any good sources showing how to incorporate the neg resistor into TF.

 
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The gain is already negative. Gain is high to model an ideal opamp with negative feedback. What is the purpose to change it to -1?

Anyone have any explanation of the (shown) simulated sample and hold function and how to calculate the sinc tf around the -10k memistor and delay line (from spice perspective)? I can calculate sinc directly, but more interested in how the tline and negative R contribute.

BTW. I can completely eliminate the opamp and still get same sinc response.
 

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Nope, please review post #1. E2 gain is positive, it must be negative to model negative resistance.

TL plus substractor is a time-continuous equivalent of transfer function f(z) = 1 - z^-1. Post #1 shows f(z) = 1 + z^-1.
 
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24BSNR said:
I would be grateful to see an example with an explanation of TF calculations for a circuit like below (f3db of sampled system etc). I can't find any good sources showing how to incorporate the neg resistor into TF.
Click to expand...
OK - here is my derivation for the transfer function:
* Let`s start with the required (known) function for SH-Block: H(s)=[1-exp(-sTc)]/sTc (with Tc=clock rate)

* We see an integration and a sum of two quantities - therefore we start with a summing integrator (most simple: inverting) with a cap as a feedback element and two resistive elements R1, R2 from a common signal input to the inv. opamp node:

H(s)=-1/RpC=-[(1/R1)+(1/R2)]/sC with Rp=R1||R2.

* Now replacing R2 with the storistor (adding a full clock period delay to the resistor):
R2 >>> R2*exp(-sTc) (series connection of a delay element and a resistor),
we can write (with R2=-R1, becaus we need a minus sign in the numerator):

H(s)=-[(1/R1)(1-exp(-sTc)]/sC=-(1-exp(-sTc)]/sTc (with Tc=R1*C) .

* This is the required function (except the minus sign)

* Note that for the inverse storistor we must write exp(-sTc)/R2 (because the delay function must be kept an cannot be inverted).

* Comment: This realization enables an inverting SH-Block only
 
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    24BSNR

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    Thanks again. PS. My first response ('you seem knowledgeable in this') was directed to you. Got confused by the reply and poster.
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Very well done. That is exactly what I was looking for. I also verified simulating a negative R2 essentially just negates or inverts the current flowing through it. So the combination of a minus R in series with the delay emulates the negative R times the emulated exponential delay (expression), exactly as in your equation above.
 
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