Interview Questions I could not answer

[scorrpeio]

I recently had a tough interview. Some of the questions were very tricky, which I could not answer...

1. In I2C, for Slave device SCL acts as input pin. Then how can slave pull the SCL line low in clock stretching?

2. How many devices can be connected in I2C practically? If it depends on capacitance and limited to 115, what is the use of 10bit addressing

3. Why we use 120ohm terminating resistor in RS485? What is impedance matching? The resistor 120ohm matches the impedance of what? What will happen if I connect 240ohm instead of 120?

4. Can I pass variables into ISR? - I replied ISR doesnt take Argument and doesnt return anything. I have got a response "Answer interms of Yes or NO. Can I pass variables into ISR?" 8-O

5. Can global variable be passed in ISR? (I replied yes.)


Can anybody tell me answers in detail? I am searching on google as well.

---------- Post added at 14:59 ---------- Previous post was at 14:56 ----------

6. In power supply design, why do I connect 1000uF 25V cap at input? What will happen if I connect 100uF and 16V instead?

7. What will happen if electrolytic capacitor is connected in reverse way? I replied that capacitor will blow. Then he asked me what is the reason?

 

[ckshivaram]

check these answers
1. When the master is reading from the slave, its the slave that places the data on the SDA line, but its the master that controls the clock. What if the slave is not ready to send the data! With devices such as EEPROMs this is not a problem, but when the slave device is actually a microprocessor with other things to do, it can be a problem. The microprocessor on the slave device will need to go to an interrupt routine, save its working registers, find out what address the master wants to read from, get the data and place it in its transmission register. This can take many uS to happen, meanwhile the master is blissfully sending out clock pulses on the SCL line that the slave cannot respond to. The I2C protocol provides a solution to this: the slave is allowed to hold the SCL line low! This is called clock stretching. When the slave gets the read command from the master it holds the clock line low. The microprocessor then gets the requested data, places it in the transmission register and releases the clock line allowing the pull-up resistor to finally pull it high. From the masters point of view, it will issue the first clock pulse of the read by making SCL high and then check to see if it really has gone high. If its still low then its the slave that holding it low and the master should wait until it goes high before continuing. Luckily the hardware I2C ports on most microprocessors will handle this automatically.

Sometimes however, the master I2C is just a collection of subroutines and there are a few implementations out there that completely ignore clock stretching. They work with things like EEPROM's but not with microprocessor slaves that use clock stretching. The result is that erroneous data is read from the slave.

2. To prevent problems with the allocation of slave addresses for new devices, it is desirable to have more address combinations. About a tenfold increase of the number of available addresses is obtained with the new 10-bit addressing.

3. RS485 uk
**broken link removed**

4. No

5. if its global it should be available in the ISR..... a global variable, say, in C, is declared outside any function, in file A, and declared extern in all other files.
Be sure to declare it as "volatile" so the compiler won't cache it in a register.
And if the variable is larger than the atomic size of the microprocessor, disable interrupts while altering the variable. Of course, in the ISR, you don't need to disable interrupts.

7. Care must be taken to ensure electrolytic capacitors are not connected in reverse polarity, if they are the dielectric dissolves which allows high current to pass though the electrolyte which will vaporize and the built up pressure will be released with the capacitor bursting open with a loud bang if the capacitor is relatively small to the sound of an explosive detonating for large filter capacitors (3300uF or so). In some situations where reverse polarity will occur a special Bi-Polar electrolytic capacitor is used.

polarization of electrolytic capacitors
Electronics/Capacitors - Wikibooks, open books for an open world

 

[scorrpeio]

Yes...that is helpful.
But in I2C, how can slave device pull SCL line low, when SCL is INPUT line to slave device? (Because a controller can change the status of output pin and not input pin.)

ALso, please tell me the difference between Harvard Architecture and Modified Harvard Architecture. (Any link will do, except Wikipedia, because I have read wikipedia but could not grasp it at root level.)

The program memory and data memory width is different in PIC (14 bit program mem and 8bit data mem). Is this why it is called as modified Harvard arcthitecure CPU?

 

[ckshivaram]

The Modified Harvard architecture is very much like the Harvard architecture but provides a pathway between the instruction memory and the CPU that allows words
from the instruction memory to be treated as read-only data. This allows constant data,particularly text strings, to be accessed without first having to be copied into data memory, thus preserving more data memory for read/write variables. Special machine language instructions are provided to read data from the instruction memory.

Most general purpose small microcontrollers used in many electronics applications, such as the PIC by Microchip Technology, Inc., and AVR by Atmel Corp. These processors are characterized by having small amounts of program and data memory, and take advantage of the Harvard architecture and reduced instruction sets (RISC) to ensure that most instructions can be executed within only one machine cycle, which is not necessarily one clock cycle. The separate storage means the program and data memories can have different bit depths.
Example: PICs have an 8-bit data word but (depending on specific range of PICs) a 12-, 14-, or 16-bit program word. This allows a single instruction to contain a full-size data constant. Other RISC architectures, for example the ARM, typically must use at least two instructions to load a full-size constant.

also see Intelligent sensor design using the ... - Google Books

---------- Post added at 16:35 ---------- Previous post was at 16:30 ----------

and about i2c..
Data is transferred in sequences of 8 bits. The bits are placed on the SDA line starting with the MSB (Most Significant Bit). The SCL line is then pulsed high, then low. Remember that the chip cannot really drive the line high, it simply "lets go" of it and the resistor actually pulls it high. For every 8 bits transferred, the device receiving the data sends back an acknowledge bit, so there are actually 9 SCL clock pulses to transfer each 8 bit byte of data. If the receiving device sends back a low ACK bit, then it has received the data and is ready to accept another byte. If it sends back a high then it is indicating it cannot accept any further data and the master should terminate the transfer by sending a stop sequence.

It is the I2c engine designed like that....

---------- Post added at 16:37 ---------- Previous post was at 16:35 ----------

As per the i2c design when we say slave.. it has I2c engine present . which have dedicated registers to monitor the start bit, individual bits of data, error flag, stop bit, ack registers.. so these registers return the status of the flow of the i2c during communication through which the device know the current status of the bus..

 

[virtualtryon]

3.The terminating resistor is used to match the characterestic impedance of wire.According to the theory of Transmission line, if impedance doen't match, the signal will be reflected and distorted which causes the telegram error. The signal quality is much more important than its magnitude.
6. The withstand voltage is low, it's choosed according to the power supply voltage. It's better to use 50% margin, that is, if the power supply voltage is 12V, it's better to use the 18V or more cap. And if the capacitance is less, your system will sustain short time during power supply drop.
7. When connected in reverse way, the internal circuit for cap is short, and produces mass heat and results in blowing.

 

[scorrpeio]

About RS232...

MCU sends signal in the level of 0-5V (mark - +5; space - 0)
However RS232 Driver converts them to +12 - -12V level (mark - -12; space - +12)

Please tell me what is the reason behind Inverse Voltage Level Conversion?

 

[luben111]

RS232 doesn't use resistive loading on the lines and is not differential so to have better noise immunity bigger voltage is desirable, it's rare to see RS232 working reliably on more than 20-30 m. In fact the standard RS232 can work with 0 and +5V levels instead of -12V and +12V. RS485 is differential and uses terminating resistors (which results in bigger currents through the lines) so it could be used for distances up to 1500 m and even more.

 

[scorrpeio]

With this I understood that to get better noise immunity over long range communication, voltage levels are shifted from 0-5V to +12 - -12V.

But why is it like 0V -> +12V and 5V -> -12V. This is an inversion.

Why can't designers did like 0V -> -12V and 5V -> +12V?
Is there any specific reason behind doing it?

 

[ckshivaram]

In rs232 communication voltage range between +3 to -3V is undefined... so there is a large swing of +3V to +25V and -3 to -25V.... these are rs232 standards..

 

[scorrpeio]

Okay...
but still one point remains...why Inversion? Why cant signal go just amplified instead of inverse amplified?

 

[ckshivaram]

there is no amplification in the voltage in rs232.....

---------- Post added at 10:20 ---------- Previous post was at 10:18 ----------

it was a standard formulated in 1960's ... read the rs232 complete technical documentation for your reference... not the web reference....

 

[luben111]

There is heavy reason why it is inverted
If the gate is non inverting it's easier to fall in self oscillating mode - during some tranition stages the input - output characteristic becomes as OpAmp with big amplification. Like result you can get much easier positive feedback and oscillations if the gate is non inverting. Non inverting gates suffer from this positive feedback so it's preffered to uses inverting gates.

So the main reason is - reliability and stability of the schematic. Invering gates are less vulnerable for selfoscillations