interview question for layout design

[mouzid]

A stupid Layout Question

I'm learning layout. I'm doing my first inverter using a pmos and an NMos transistr from the library. I know that the pmos bulk have to be connected to vdd, the nmos bulk to gnd. That is not clear for me in the picture sowing the layout of the 2 transistors. I drawed the layout of the inverter, but I dont know to connect the bulk of the pmos and the nmos.
Please help.

 

[ljy4468]

Re: A stupid Layout Question

The layout program must be virtuoso, & right green area should be nwell region.

In virtuoso, the black background is substrate.
If you use p-substrate process, then all background (black) area is p-sub.

And now, in NMOS case, there must be p+ region for sub-tie.
So you can draw p+ diffusion & contact at p-sub near NMOS. And connect that to gnd. this is body bias for NMOS.

For PMOS case, you should draw n+ diffusion & contact at n-well region near PMOS. And connect that to vdd. this is body bias for PMOS.(well-tie)

Here is the example.
upper side is PMOS.



Regards.

 

[AdvaRes]

A stupid Layout Question

Hi ljy4468,
Your inverter will not work. I dont see bulk connection to vdd and gnd.

Look at the picture below. It represent a nice Inverter. I picked it from
https://www.eda.ncsu.edu/wiki/Tutorial:CDK_Layout_Tutorial

 

[ljy4468]

A stupid Layout Question

What is the difference between yours & mine?

The only different thing I can find is
-your tap is located at left side
-my tap is located at bottom(NMOS), at top(PMOS)

I don't understand why you cannot find bulk connection.

And I got fab-in some circuit with above inverter, and It ,of course, operates well.

Point out if I'm wrong,

 

[AdvaRes]

Re: A stupid Layout Question

What is the difference between yours & mine?

The only different thing I can find is
-your tap is located at left side
-my tap is located at bottom(NMOS), at top(PMOS)

I don't understand why you cannot find bulk connection.

And I got fab-in some circuit with above inverter, and It ,of course, operates well.

Point out if I'm wrong,

Maybe I'm wrong. I think that your inverter is not done using Virtuoso.
Diffusion colors are different if compared to the second layout.

Concerning your tap, I see them up and down but shouldn't it be close to the diffusions ?

 

[ljy4468]

A stupid Layout Question

Ok, I layouted with virtuoso.
But display.drf maybe different from yours. Users can change color of layer.

And tap and diffusion should have a little clearance according to my design rule.
Also, in some process, that can be adjacent as your layout.

Regards.

 

[myhaqita]

Re: A stupid Layout Question

so means that guard-band which consist of n+ layer (for PMOS) is also consider as bulk? so i can connected the guardband to vdd rite?it still give the same connection as yours rite?

i am new designer..thanks

 

[keith1200rs]

Re: A stupid Layout Question

Hi ljy4468,
Your inverter will not work. I dont see bulk connection to vdd and gnd.

Looks fine to me!

Keith