Interview question about a FIFO depth

[dazzling_deepika]

i have a question that is asked in an interview . i am writing into fifo asynchronously with 25 writes per second and reading form fifo with 25 reads per second synchronously. then what the depth of this fifo?


My answer is no fifo required..am I correct?if not please explain the right ans

 

[anant]

interview question fifo depth

I dont know if this is the right section for these types of questions.

anyways my answer is 25 .

 

[lakshman.ar]

determine depth of fifo

Not needed !

 

[ray123]

fifo depth, digital design questions, answers

my answer is 25.
This is based on the worst scenario.
In one second, all 25 writes could be issued before any read.

 

[sanjay11]

interview question + fifo depth

if it is asynchronous write and read .... the clocks may differ by phase and ppm (ppm) difference.

Based on that fifo may be needed.

 

[yx.yang]

parts per million fifo

My answer is 50.
write: 25(last second back) + 25(next second head) = 50). Then, read.

 

[vivek4m]

depth of fifo

to avoid an overflow, you need the depth to be 25 atleast!

 

[fybh911]

fifo depth

50

 

[feel_on_on]

fifo depth question

50 at least

 

[rakko]

Re: fifo depth question

If the 25 writes and 25 reads are certain to happen, then you don't need a fifo. just a small elasticity buffer. the size depends how far can the two clocks drift in 25 cycle. For the worst plls this is not more than a few locations.

 

[basilmk]

Re: fifo depth question

I need to design a FIFO
write speed - 216Mhz

read speed - 324 Mhz

Data rate - 74.25 Mhz

wat depth will i need ?

 

[kalaiyarasan]

fifo depth question

can be more specific

 

[pradeep2323]

Re: fifo depth question

no need of fifo,

but if u want to support for worst case scenario also then it should be 25

 

[basilmk]

Re: fifo depth question

thx 4 de rply..

actually i had got ma task wrong ..

..lemme try restating Q :

i got to design a block that has got one incoming clock domain at 216 Mhz , another outgoing clock domain at 324 Mhz..

now, i have a 1 bit valid signal at 74.25 Mhz.. ( it basically means.. for example in clock 1 domain , the data will be read only when the valid signal is high .. similarly for clok 2 )

what i need is to find out the depth of FIFO, so that valid signal has same data rate, in the outgoing domain too..

 

[lostinxlation]

Re: fifo depth question

I don't know what it means by "asynchronously write".
But assuming the read and write clocks are off in frequency and you need a async fifo, you have to remember the pointers are required to be double flopped to cross the clock domain, so that the data written now won't be read to the read agent until 2 read cycles later, while the write operation could continue in the meantime.
So, I guess no fifo required is clearly a wrong answer. May be the worse case is 25 data is written within 1 read cycle, and then 1 second later, 25 burst write happens again. In this scenario, you need a little over 25 entries in FIFO( I think 27 or 28 entries ?).

 

[anoop12]

Re: fifo depth question

It depends when the read is initiated after write.
Minimum is 25.

 

[woshicloud]

Re: fifo depth question

the size is decided by the biggest latency of specific write to read! 25 or 50 are not right answer!

 

[sdwsh]

fifo depth question

at least 50 is needed