interstage gain in pipelined adc

[ljy4468]

hi everybody
i don't know difference between interstage gain 3 and 4.

Interstage gain is residue amplifier gain..
e.g.) 1stage with 1bit resolution's gain is 2
and 1stage with 2bit resolution's gain is 4(2bit mdac gain)

but i've confused what's difference 3 and 4.
I know 2.5bit mdac is implemented with 6comparators(7 levels)

BUT, in "A generic multilevel multiplying d/a converter for pipelined ADCs"
-vivek sharma
there are 5levels mdac (000,001,010,011,100)

If i using 2stage pipelined which have 7level each stage (interstage gain=4)
output will be 4bit.
and using 2stage pipelined which have 5level each stage (interstage gain=3)
output will be 4bit.

What's the diference????
i'am very confused.
anyone give me answer

 

[sunking]

the output of pipieline will be modified by digital circuit. read the paper more you can get the reason