internal structure of 8279

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does anyone know the internal structure of the 8279 programmable keyboard controller? not the block diagram i know that one. i need the complete schematics with all the flip-flops and everything...
 

Contact Intel but don't expect cooperation, I doubt they will give you the information you want as it would be copyrighted.
There are probably thousands of gates inside such a device, it would be almost impossible to replicate in individual components, why don't you use a real 8279 or design something for yourself?

Brian.
 
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    Klinec

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well i wish i could use the 8279, but it's for uni project and we're forbidden to use ready components such as 8279, just flip-flops and gates, and some standard components for ram and rom, like 8185, 8255 (is the one exception that we can use). the project is to interface a 103-key keyboard to an 8086 microprocessor. any ideas?
 

Trying to mimic the 8279 would be my least favored solution, it is a very good device but not optimized for your specific purpose.
For 103 keys, if you arrange them in a matrix, you only need 11 control lines to read them in a 10x11 array, you would have 8 keys left over for other purposes. If you can use generc logic circuits, you can achieve this with two 4-bit ports, each decoded to one of 16 lines. If you drive one of 16 lines into the matrix and receive a key number back on the other 4 lines you can read 256 keys using only 8 signals. You could therefore use something like a PIC16xx IC to scan all your keys and it could return the data in almost any format you want. It's a one chip solution abd costs very little.

Brian.
 

Hi,
I think that 8279 is a preprogrammed version (ROM based) of UPI-41/A.
Or Universal peripheral interface 8041/A, 8641/A, 8741/A, etc.
It is similar to UPI-42 or 8042, 8742.
It is based on MCS-48 or 8048, 8748, 8049, ….., etc.
UPI-41/42 was used in the keyboards of IBM PC.
I hope that will help.
Regards
Petre Petrov
 

the opencores.com website has some open source keyboard controllers in VHDL/verilog.
I have used one of them on an FPGA.
You can check their source code to see what they do internally. And either re-implement, or re-use.
 

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