Internal RC oscillator for reliable USART

[valdorf]

I want to use microcontroller - STM32C011F6P3TR.


As mentioned in datasheet, it has internal 48 MHz RC oscillator (±1 % accuracy).Can I use this microcontroller without using external crystal for USART communication at baudrates up to 57600?I want to reduce number of external parts to save space and price.

 

[barry]

You need to do a timing analysis. WE don't know what your USART is connected to.

 

[valdorf]

You need to do a timing analysis. WE don't know what your USART is connected to.

USART will be used to communicate with another device using Modbus RTU protocol (RS485). RS485 configuration: 57600 8E1.

 

[KlausST]

Hi,

As Barry says ... you need to do timing analysis:
Consider:
* according to baud rate divider in the STM32 you get an baud rate error (fixed error)
* you get a baud rate error by the STM internal oscillator (drifting)
* and the errors in the communication partner

I´m sure there are STM32 application notes discussing UART communication
And there are documents for general UART discussions

Klaus

 

[FvM]

+/- 1 % is perfect for standard UART. Even +/- 3 % can work. Notice that STM32 1 % spec is valid for 25 °C only. Additional frequency error can be caused by applying mechanical forces to the package, e.g. due to PCB warping.

 

[D.A.(Tony)Stewart]

To prevent a timing error the stop bit state must occur within 10% of the time for 1b start + 8b + 1b stop = 10 bits, all of the time for 10^n bits.

The total stackup error includes;

1. the oversampling clock resolution. Usually 1/16 b for a 16x clk.
2. the Tx % error in f
3. the Rx % error in f
4. the initial tolerance error and drift due to expected operating range.
5. any sensitivity error due to Vdd tolerances expected.
6. any noise that shifts the phase of the start or stop bit from the amplitude variation yet detected by a comparator near 2 diode drops, the standard for all TTL in spite of the +/-V levels.
7. any ISI or Inter Symbol Interference due to filters or the transmission path not necessarily included in an uncontrolled environment with transient and random interference.

The spec for tolerance error is uniquely defined by the designer for the intended use case.
If the environmental for use is limited and fixed, part of the design must include a test plan to vary the limit to the limit of failure with low voltage and noise present to ensure there is sufficient margin for the expected and perhaps the unexpected such as a very long cable capacitance.

For trivial cases, the designer may choose to do more or less and just inject conducted pseudo-random noise to some SNR p-p level such as 16 to 20 dB or do nothing at their peril.

Most people ignore parity bits, but this adds free reliability if there is adequate margin in the bandwidth and timing margin while the Rx pays attention to fault codes or has a robust error detection/correction routine.

--- Updated Apr 24, 2024 ---

One more thing on tolerances. ( or many)

It is important to remember that with ANY spec, the limit point of failure MUST EXCEED (be better than) the published spec.

[Normally, there are actually several spec levels per a good design specification;

1) component spec (the tightest),
2) assembly build test spec (a little looser spec),
3) final test limit (looser still but better than published) and
4) published spec for the user (guaranteed that ALL units, in the hands of ANY user will perform to the published spec).

yes even 3% is perfect (iff the overall stackup meets spec)

 

[dick_freebird]

Are you receiving a companion clock from the same
source as the data, aligned ideally? That would be best.

Otherwise you have to recover clock from data and that
gets busy, quick.

 

[D.A.(Tony)Stewart]

This is how UARTs work. Sync bit on Start edge, confirm at midbit, then stored every bit x clocks later where x= is normally 16.
So since you have at least 10 bits per word, the worst case is 10% freq error or +/-5% f.

Synchronous streaming data without start or stop bits uses a PLL to lock onto data intervals by measuring phase error of a transition, then sample bits with the clock edge that is in the midbit position.

Other physical protocols supply Clock & Data to simplify the reception but still require word & frame sync clocks.

If both Tx & Rx are limited to 3% error each then 4% is your worst case error margin for all system noise, supply and ISI disturbances and asymmetry due to unequal source impedances for 0 or 1 if using RS-232 is usually OK. Although I recall University days in early '70's used 9600 baud across a large campus and due to crosstalk, selective wire pairs were excluded in a large bundle of pairs by test results on error rate.

 

[valdorf]

+/- 1 % is perfect for standard UART. Even +/- 3 % can work. Notice that STM32 1 % spec is valid for 25 °C only. Additional frequency error can be caused by applying mechanical forces to the package, e.g. due to PCB warping.

It is okay 25 °C, because device will be used in a room temperature.