Internal Gate Resistance Measurement

I am wondering if anyone has any good documents on the internal gate resistance of a MOSFET.

I am searching for a way to measure it.

We know it exists, but other than it being listed in the datasheet there doesn't appear to be much information on its behaviour:
- how can we measure it?
- what is its behaviour in circuit?
- what are the material properties that influence it?
- how does its value change with aging?

The only good document I can find is this: https://www.st.com/st-web-ui/static...ical/document/application_note/DM00068312.pdf

But the conclusions this makes are fairly logical - a higher internal gate resistance means higher switching losses and higher chip temperatures.

I would like to find a way to measure it when the MOSFET is in a converter. I have read jedec standards about using an LCR meter and also methods that say I have to short the drain and the source - but I don't think that helps me.

I think it should be possible - these values seem to be in the range of 1-10ohm. Surely the peak gate current is related to it? I could just put a 2V on the gate and measure the peak gate current and infer it from this? But then the parasitic capacitances and inductances also have an effect? I could infer it through modelling if I have actual switching waveforms (this could get complicated and I would need accurate measurements of a lot of variables)

Ultimately I would like to find a way to do this while the MOSFET is in an operating converter

the only easy way i can think of to measure it is to use a signal generator, current transformer and an inductor on the order of 1 uH to excite the gate as an LC resonant tank, then measure the bandwidth. or if you can pulse the signal transformer, you can watch the impulse decay and infer from the rate of decay. you will have to know the parasicic resistance of the inductor, but an air core litz wire inductor can have a negligible value here.

anyhow, as to measuring it in circuit, i suppose you could wrap a high bandwidth rogowski coil around the gate drive lead, and using a common Oscope infer the extra resistance that is added to the known gate drive resistance, and calculate the difference. assuming the parasitic inductance is negligible.. which it hardly is.

If you refer to the simplified "Internal parameters" circuit in the application note, an LCR meter measurement would be the straightforward way. In the real power components world, there are more parasitice elements and Rg will be distributed, as already discussed in AN text. But the LCR measurement would still allow to determine type and temperature variations of Rg. You also may want to check if reverse biasing of the MOS capacitors gives different Rg values. If so, you can select a bias point that corresponds most closely to regular switching operation.

Although I agree that Rg can be measured in switching operation, you would make your life unnecessarily hard by struggling with the huge capacitance non-linearity. I also don't see the advantage compared to a static measurement. At the end of the day, the gate drive of the circuit will be adjusted for optimal switching behaviour, reduced EMI, moderate overvoltage, whatsoever. In most cases, this is done by adding artificial gate resistance extern to the MOSFETs, possibly asymetrically. All transistor parameters are howver type and temperature dependent. So knowing only the Rg related variations won't bring you far.

FvM said:

If you refer to the simplified "Internal parameters" circuit in the application note, an LCR meter measurement would be the straightforward way. In the real power components world, there are more parasitice elements and Rg will be distributed, as already discussed in AN text. But the LCR measurement would still allow to determine type and temperature variations of Rg. You also may want to check if reverse biasing of the MOS capacitors gives different Rg values. If so, you can select a bias point that corresponds most closely to regular switching operation.

Although I agree that Rg can be measured in switching operation, you would make your life unnecessarily hard by struggling with the huge capacitance non-linearity. I also don't see the advantage compared to a static measurement. At the end of the day, the gate drive of the circuit will be adjusted for optimal switching behaviour, reduced EMI, moderate overvoltage, whatsoever. In most cases, this is done by adding artificial gate resistance extern to the MOSFETs, possibly asymetrically. All transistor parameters are howver type and temperature dependent. So knowing only the Rg related variations won't bring you far.

Click to expand...

I am interested as its a parameter I can't find much to read about. I agree that it seems largely ignored or irrelevant as a 20ohm external gate resistance probably has much more of an influence than a 2ohms inside the MOSFET/igbt. Originally the idea came from working with silicon carbide and the oscillations we get on switching - how would device parameters change after 5 years, would these oscillations reduce over time or get worse. I've also seen documents suggesting we can use oscillations during swithing of IGBTs to indicate wear-out.

Regarding capicitance changing - i know the capacitances change during the actual switching transition and actually I just leave this out and assume an average when looking at the formulas. But if we measure during the OFF state, aren't all the capacitances constant? And if not, I was thinking that during the measurement I can add artificial fairly large external capacitors for Cgs that make the parasitic fluctuations largely irrelevant, if indeed capacitance influences my results (I already know this is added in in some 'intelligent' gate drivers). Perhaps these fluctuations rule out inferring Rg from switching waveforms however - but I always thought this would be more complicated anyway.

What capacitances do I specifically need to be aware of while measuring Rg? Is it just Cgs? I probably need to have a measurement time of less than 50us, then it could be feasible to do this measurement during the OFF state of a MOSFET in converter and so the measurement itself doesn't induce self-heating etc - lets say the converter has a switching frequency of 5khz or similar.

I also looked at trying to measure these capacitances during operation, but decided that Rg would be a better place to start with values of 1-10Ohms rather than pF. I also been reading that these capacitances don't change with temperature? (seems strange to me but I've seen this written in a few application notes and would have thought this would have been clarified after several decades of using power semiconductors)

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Johansen said:

anyhow, as to measuring it in circuit, i suppose you could wrap a high bandwidth rogowski coil around the gate drive lead, and using a common Oscope infer the extra resistance that is added to the known gate drive resistance, and calculate the difference. assuming the parasitic inductance is negligible.. which it hardly is.

Click to expand...

So this is kind of like what I said when I talked about measuring peak gate current?

I was not thinking of doing this on the actual gate driver current - rather for the measurement I would have a separate very well characterised circuit that applied a gate voltage lower than the threshold voltage during the device's OFFstate and measure this peak current. I don't think it matters if the measurement is slightly inaccurate, as long as it gives the same each time - ie if its 1.5ohm out, it gives a value 1.5ohm out every time so the measurements are the same in relative terms

You might look at turnoff dV/dt with a very low (and
known) on-resistance FET driver, and the same driver
with a small series resistance interposed, and then
extrapolate to infinite dV/dt (probably using the inverse
dt/dv and extrapolating to zero) - your drain dV/dt
followd Cds and Rg(total), any residue on the fit is
internal Rg.

Though I'd probably just skip the math and fit in the
simulator using parametric analysis and eyeball.

This testing only needs an oscilloscope (dV/dt) and
DMM (driver baseline on-resistance).

The S, D terminal impedances need to be relatively
low to keep those from limiting turnoff.

i have a few fundamental problems with some of the material in the attached paper in the first post.

A high internal resistance mosfet should still have some of the mosfet cells turned on when the gate is pulled high, effectively instantly; i recall reading that the actual switching time for a single mosfet cell is on the order of 500Ps.
So when the first few cells turn on, they are going to effectively be exposed to extreme harsh conditions. current is limited by the on resistance only, which is fine.
but if the first 10% of the cells to turn on are enough to fully commutate the converter, are you going to notice the performance degrade?

so suppose we have a mosfet with 10 times the distributed gate resistance as another.
and if the average distributed resistance is the same as the gate resistor.
then it will only take twice as long to fully turn on.

now granted i understand that when we're dealing with 4 ohms of gate resistance, 5-30nH of source and gate lead inductance, 1-5nF of gate capacitance and 0.5-1nF of miller capacitance, the distributed gate resistance is going to be rather hard to separate out from everything else.

I'm not sure I understand your post. I thought increasing the external gate resistance or increasing the internal gate resistance would cause the same behaviour changes?

There is something about propagation delay in Baliga's "Fundamentals of Power Semiconductor Devices" on page 434 which to me indicates there could be some behavioural differences depending on which gate resistance is increase - but i dont know

How did you make the assumption that 10x the internal gate resistance only leads to a doubling of turn on time?

These parasitic capacitances also depend on Vds, so they actually change a lot DURING the switching transition. I think it is a bit wild of me to think I can calculate internal gate resistance from switching waveforms - seems like a whole PhD and post-doc could be on it. If I was going to go that way, I think I could slow the switching down, or do some sort of Vgs sweep, or something - add my own larger capacitances to make this nF negligdable

I think realistically I am looking at developing a way to measure it when the MOSFET is in the OFFstate - this way I could measure it every single switching cycle if I wanted (providing the measurement doesn't induce unacceptable noise or disruption to the converter operation). But I have to think carefully about what will influence the measurement in order to make it robust, so so far I am thinking:

- parasitic capacitances: these may change as the device ages, and with temperature?
- the gate is connected through a bondwire - this definitely ages and changes with temperature
- switching frequency?


Do you have any material that explains 'distributed internal gate resistance" for power MOSFETs? I really can't find much

I think my idea of applying a voltage below the threshold voltage during the MOSFETs off-state and measuring the peak gate current COULD work - certainly in my rough LTSpice simulations, the converter still seems to work and this current is dependent on me changing the size of the gate resistance in the model. When the current is flowing through the body-diode though the gate current starts going AWOL - but I don't think that matters that much in the average inverter, I can just make the measurement when I dont have the bodydiode conducting. I think I need to know literally everything about the MOSFET though to infer the internal resistance from this - its not just a case of V=IR (although this doesn't give a value THAT far off).

i only assumed that the internal gate resistance is on the order of a square grid of capacitors from gate to source, capacitors connected to the drain, and connected by resistors.

the bond wire could be connected to the edge of the square grid, or in the center. all the ones i've seen the gate bond wire is connected to the corner.

suppose I have two mosfets. both have 10 ohm external gate resistances.
once has an internal distributed gate resistance of 10 ohms. the other only 1 ohm.

its obvious to see that the 1 ohm fet will fully turn on much sooner than the 10 ohm fet, but the peak current though the gate drive resistor won't be much different.
because the capacitance is distributed, the initial peak current might even be nearly the same. but a graph of current vs time should show drastic differences.

Gate resistances specified in datasheets are obviously measured with the JEDEC standard LCR meter method, as the measurement frequency annotation clarifies. Thus I think, all measurements exploring type and temperature variation or possible wear should refer to the same method.

I agree that the distributed nature of internal gate resistance must be expected to show in switching operation. Also the strong capacitance nonlinearity and terminal inductance will make it difficult to relate measured switching timing to gate resistance and other parameters.

Yes I will start with the LCR meter. But I cannot use this in the circuit during the MOSFETs off-state

So what you are saying is that putting Vgs to 1V and measuring peak current is not going to be simple in the real world - perhaps the peak current won't even change a measurable amount from changes in internal resistance due to temperature during operation? Even if I made a highly calibrated and compensated measurement system?

So I would need to track the peak and current over time - still it would not be as simple of a calculation as I would like it to be. I will have to investigage what are the exact influences on gate current if Vgs is below threshold voltage. But in a highly calibrated measurement system I should at least know the parasitics in my measurement system to a good accuracy, maybe the parasitics of the individual mosfet/module will be harder and especially if they change over time