imbichie
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Hi All,
I am using Synplify Premier I-2013.09-1 for Xilinx Virtex5 XC5VLX330 synthesis.
Its compiling and pre-mapping well.
But during the Map and Optimization, its showing this error:
Error Code [nlverify.c:5742 Found functional mismatch inside module top_module_name]
While running 64-bit - Linux build
@E: Internal error in m_xilinx
Is there any solution for this?
Whether I did anything wrong?
My design is fine with Simulation.
I am using Synplify Premier I-2013.09-1 for Xilinx Virtex5 XC5VLX330 synthesis.
Its compiling and pre-mapping well.
But during the Map and Optimization, its showing this error:
Error Code [nlverify.c:5742 Found functional mismatch inside module top_module_name]
While running 64-bit - Linux build
@E: Internal error in m_xilinx
Is there any solution for this?
Whether I did anything wrong?
My design is fine with Simulation.