Interleave phases , multiphase converter..

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Trishool

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Dear Members;

I need to design a DC-DC isolated converter the Dc bus voltage is 50VDC and I want to interleave the current (500Amps) to 10 channels . Then it should be 360/N channels , my question is can we select a longer timeperiod say 720degrees/N . It might sound ridculous.

I also need to clarify , in boost PFC/CCM when we tend to interleave the channels then do we design the system similar to ON/OFF gated at 360/N equivalent timeperiod or do we let the inductor trpezoidal waveform overlap as in the case of 3phse system.

Thanks in Advance...
Regards
 

I'd recommend a 10X clock reference and a Johnson counter
(CD4000 series used to have a decade Johnson counter).
 

Trishool said:
my question is can we select a longer timeperiod say 720degrees/N . It might sound ridculous.
Click to expand...

We can put it in other terms by starting with 100 percent of a cycle. It is the same as saying 360 degrees. We come 'full circle'.


It is common for the coils to have overlapping 'On'-times and/or discharge times. (Although not every case requires it.)

Here is a simulation showing the waveforms in a multiple interleaved boost converter. It draws about 500 A from a 50 V supply.

 

dick_freebird said:
I'd recommend a 10X clock reference and a Johnson counter
(CD4000 series used to have a decade Johnson counter).
Click to expand...



Thanks for the reply, please advice me what is the case which require overlappin?

I also need to know for sinus signals sequencing in 'N' number of interleaved channels. Do we start and stop the cycles in each channel, every 36degrees added intervals for each channel one after another. OR we have to maintain the 10 phases sequence . Can it be gated on/ off in sequence?

Rgds
 

Isolated means separate transformers for each channel?
With 720/N, you have channel pairs of identical phase. Apparently no difference to 360/N (for even channel number).

Schematic + waveforms can possibly clarify what you want to achieve. If the channels are operating in CCM, currents will always overlap, I think. Where do you expect trapezoidal currents?
 


Plan on turning coils on at equal time intervals (tentatively, if all coils are the same).

Additionally your control circuit must be able to turn off each coil after a >> variable << time period.

In other words, you need to be able to adjust the duty cycle. For instance, your duty cycle might need to be 63 percent. You would switch On coils #1 through #6 in sequence, and then you turn #1 Off 3/10 of the way between turning on 6 and 7.

All ten coils will receive the same duty cycle (tentatively).

So it becomes a question what is the simplest, easiest (and yet reliable) way to implement controls to your switching devices.
 

Please accept my apologies , I couldnt reply earlier .....




Yes separate transformer, and its excited with a full bridge (4 MOSFETS). I am exploring this , so I have not yet com up with schematics.

If we drive the MOSFET channels , is it necessary to complement the PWM on alternate channels , or can we leave the high side MOSFET ON and vice versa.

When these 6 different full bridges are required to be interleaved , how to attempt this , do we have to keep the sine wave frequency very high say 10KHz , what is
recccomended.




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could you advice me some pseudo code to implement this. What should be done multitasking / or wih ISR.


Regards
Ts
 

You metioned an isolated DC/DC converter and also a boost PFC in your initial post. About which part are you asking now?

A DC/DC converter might vary pulse widths for voltage control, but not use PWM to generate waveforms, thus the H-bridge not switch more than once during a half-cycle.
 


Its two stage BOOST ----> Isolation. I think you misunderstood me . I mean using only 2 PWM channels for H bridge and the rest high side Fets to remain in on/off state (Pls find below image).

[
 
Last edited:

Trishool said:
could you advice me some pseudo code to implement this. What should be done multitasking / or wih ISR.

Regards
Ts
Click to expand...

This simulation is an example of how you would apply ten clock signals on and off in sequence.



It is based on the duty cycle being 77 percent as in my post #3. However it could just as well be 67 or 87 percent. Hence you want your control device to be able to alter it easily, no matter whether the signals are generated in hardware or software.

The simulated switches are useful to portray which ones are on or off. As you can see, only two or three switches are off at any one time. (A real project will have mosfets or transistors instead.)
 
This simulation is an example of how you would apply ten clock signals on and off in sequence.
Click to expand...
Yes, but where's a place for sine PWM according to post #9 in the design?
 

\\\\\
Thanks for the clarification, here can we assume that the isolated section of each phase will work in accordance with it indirectly(Dc o/p) . Do you say nominally the the duticucle should be at 67 or 87 percent.
 

FvM said:
Yes, but where's a place for sine PWM according to post #9 in the design?
Click to expand...

I am getting the impression there is more going on in this project than I realized.

I cannot figure out whether all functions are combined into one operation, or whether the project needs to be split up into several functions (and perhaps several threads).
 

Trishool said:
\\\\\
Thanks for the clarification, here can we assume that the isolated section of each phase will work in accordance with it indirectly(Dc o/p) .
Click to expand...

I suppose I got an incorrect idea as I read your initial post. It sounded as though you want a single supply to power ten interleaved boost converters, with a combined output of 500 A.

Now I am confused, since your later posts bring up 3-phase, transformer, 6-mosfet array, and an H-bridge.

Do you say nominally the the duticucle should be at 67 or 87 percent.
Click to expand...

I should have said the duty cycle is as likely to be in the 60's or 80's. It only means that you will not necessarily switch Off coil #1 between switch-On of coils 7 and 8. It might be between switch-On of coils 6 and 7, or between coils 8 and 9. It complicates the design and construction of your control circuitry.
 


Sorry for the confusion, I attach a block diagram for clarification below;

What I mean is the each interleaved section is isolated too. So when the boost stage gets interleaving signals , its asociated HF isolation stage indirectly works in acordance. Is this ok, or we need multiple sections .
 

It would be better to have all the boost phases tied directly in parallel, that way they can share input filters and output DC capacitor banks, which should lower the overall ripple seen at the inputs and outputs (assuming they are phase interleaved). I assume all the DC-DC stages will be in parallel as well, with one output bus.
 


I was wondering if 10phases interleaving is a practical thing to do ..... can somebody advice me regarding its practicality.
 

6- and 12-phase circuits are quite common in power electronics, feasibility isn't the point.

I agree with mtwieg that sharing the DC busses in a multi-phase parallel design is advantegous to reduce ripple currents and save capacitor size. However, paralleling smaller inverter's in- and outputs still reduces ripple currents and lower PWM frequent harmonics, when the PWM generators are synchronized and phase shifted. In so far it's the next best solution.
 


True. What I was thinking was whether dividing it into 10phases would substantially reduce the ripple current ? . I mean not doning the extra effort if say the efficiency only improves marginally after 4phases... This thing I am not sure .
 

Well that's when you have to start doing some maths, and some preliminary design. IMO that many phases probably won't be necessary unless you're trying to push out at least 1kW through each.
 

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