interfacing between Customized AXILITE master block to DDR3 using Microblaze

yayasinjab

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Hello Everyone,
I am trying to send data from an RTL block I have to my DDR3 memory to be stored there. (I dont need to read them from my Custom AXI block).
Process is as follow: custom AXI to microblaze to DDR3 to ethernet to display.

I have done editing the template provided by xilinx of Master AXILITE. and when i am checking the address editor tap, it showed that the mig memory is part of my AXI block list as shown in the photo. However, when i am reading the data, it shows no data change in the memory. So I used ILA for the bus of AXI connection between my AXI block and AXIinterconnect, and this is the results of each channel using ILA.

Basically, there is no response from the axi Interconnect, and I am really confused why is that happening, it will be really appreciated if someone can share his experience with me please.









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One more thing, whenever i am writing to the memory using C code, using SDK, it is working, and i can read the data properly.
 

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@yayasinjab
Where is your behavorial simulation model? Where is your testbench?
ILA is not the correct debug strategy for such problems. Please simulate your design first and then come back.
 

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