;.equ baud_const, 0 ;automatic baud rate detection
.equ baud_const, 244 ;9600 baud w/ 22.1184 MHz
PAULMON2 Loc:8000 >
PAULMON2 Loc:8000 >
Help
Standard Commands
?- This help list
M- List programs
R- Run program
D- Download
U- Upload
N- New location
J- Jump to memory location
H- Hex dump external memory
I- Hex dump internal memory
E- Editing external ram
C- Clear memory
User Installed Commands
PAULMON2 Loc:8000 >
Using C52-EVB method. Can the Keil compiler link to C52-EVB board? Which mean when the Keil is Start Debug debuging the C code at the same time C52-EVB will start simulate the haarware as well. So, we can real time debuging the result. Is it possible?...during in monitor mode that runs under PAULMON2...
How to download hex file to SRAM? What does the sentence mean Begin ascii transfer of Intel hex file, or ESC to abort. This message is for D-Download command. What should we type after this sentence?
no probles, file transfers without errors ..Please can you try for me the hello.hex
I can't get 64Kb SRAM in my cityUsing bank switching (and some extra ‘logic’ to combine PSEN, RD, WR and one available pin, for example, P1.7) it’s possible to connect two 64Kb memory banks (BANK1 and BANK2) to contain code memory giving a total of 128Kb ..
For this concern, When initialize power up the P1.0 and P1.1 will set to '1' to select U3 as PAGE1. I'm not sure is it correct not?Also, it is possible to use a 128Kb SRAM chip (as BANK2 in the above example) and take A16 address line from another P1-pin, for example, P1.0 ..
After power up or reset P1.0 is set to ‘1’, thus access is to the upper 64Kb, that is page 1 ..
Actually i more like to use new technology or new method to do so..I'm get used to it on 8051/52. I'm not sure whether got any target is more then >64kB. I think temporary using small MCU for my hobby and easy for me to source the MCU and burner in my city.However, I'm curious as to the reasoning behind implementing bank switching (‘old’ approach) rather than to switch to a processor with a larger address space?
Do you mean half of the BANK2 memory is use for CODE and another half is for DATA memory and also can be I/O port's?where BANK2 can have two 64Kb pages and it can also be used as DATA memory ..
In addition, there are 4 memory-mapped devices such as 32/64Kb DATA memory or I/O port(s) ..
Yes, why not ..Temporary, is it possible we start on 32Kb SRAM?
Somewhere at the end of the code in BANK0:How the P1.6 do the switching?
; Switch to BANK1
ORG 0FFFBh
Switch_Bank_1: CLR P1.6
; Switch to BANK0, BANK1 = 32Kb
ORG 07FFBh
Switch_Bank_0: SETB P1.6
The BANK0 is it a ROM? Why the A14/A15 is on the same pin? and How come the A14 have 2 pin on one IC? It share with the A14//WE? and Why need jumper for A14/A15 and A14//WE?
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