Interface Verilog Custom Core To Read and Write From DDR RAM

[aibk01]

I want to add a custom verilog core to an already established pipeline of microblaze. The core should be able to read data from memory locations from DDR RAM (external) which is already present on PLB, process it i.e add to value of data and replace the data it has read with the new processed data. In short i want to add certain constant number to data on RAM in a parallel fashion,(video frame) and write back to those very locations.

Please guide me how should i go about. Should i create a custom peripheral?

Should i use FSL?

As i am new in this field kindly guide me!

Thank You


I am using Xilinx Spartan3E 1600.

With ISE and XPS 10.1 sp1