interface FPGA to GPMC

Hi all,

This is M.Subash from bengaluru. I am new to GPMC. I would like to interface FPGA to GPMC. In GPMC side, all clk and datas are coming perfectly. i can't write the correct data into the fifo in fpga side. Kindly let me know that how to interface FPGA to GPMC and what are the IO Pins required to interface.


Thanks and regards,
M.Subash

new to GPMC

Click to expand...

What does the acronym GPMC mean to you?
Make sure you have the correct synchronisers/strobes in place when dealing with memories operating in different clocking domains

Hi wesleytaylor,

GPMC(General Purpose Memory Controller). In GPMC side, all signal coming perfectly. we checked with another board. But now we want to interface with FPGA. I can't write the correct data into the FIFO in FPGA side. so i want to know that how to interface FPGA with GPMC. Kindly let me know that..


Thanks and regards,
M.Subash

M Subash,

I've not used or written anything for GPMC, however what I recommend having a look here
https://groups.google.com/forum/#!topic/pandaboard/2t1uIB6zfds

M Subash said:

GPMC(General Purpose Memory Controller). In GPMC side, all signal coming perfectly. we checked with another board. But now we want to interface with FPGA. I can't write the correct data into the FIFO in FPGA side. so i want to know that how to interface FPGA with GPMC. Kindly let me know that..

Click to expand...

An FPGA is a blank sheet of paper that needs to be programmed with whatever logic you want. You have to write VHDL or Verilog code for the FPGA. Since nobody here knows anything about your design you won't get specific help. But here are some guidelines:
- Create a simulation model for your GPMC interface that operates as shown in the datasheet for whatever device that has this GPMC interface.
- Create a testbench that instantiates your FPGA design code and the simulation model for the GPMC interface that you just created.
- Run the testbench to make sure that the FPGA is responding as you expect
- Verify that static timing analysis of the FPGA design is successful.

If things are still not working, then come back here with more specific targeted questions. Statements like "GPMC side, all signal coming perfectly. we checked with another board" and "can't write the correct data into the FIFO in FPGA side" are meaningless. Nobody here knows:
- What specific GPMC interface you're referencing
- What is the 'another board' that you checked?
- What environment is your FPGA in? Is it in a commercial board (which one?), or your own design?

Kevin Jennings