ad9826
I have started to develop interface, but it is a leatle bit slow process since I am working on my PhD. But if You would like we might be at contact.
My idea is this: Clock is generated from CPLD, be careful about the clock conditions. There is a good explaination about the timing on page 8 of datasheet. Shutter is opened from falling edge of SH to next falling edge of SH, after that on rise of ICG You start to readout a CCD.
My idea is to put AD9826 (I recomend You to visit
www.analog.com) to collect data and then to feed them to sram.
I suppose that, for this veekend I will try to finish a test board just to see the shape of the output signal. From that I shoud decide if it is necesery to use ICG mode or not of AD9826. Currently I have just done the frequency dividers in verilog and I am planing to work a leatle bit more as soon as my calcu;lation starts to yield some useful results (indetermined time, but I hope soon).
If You would like I might send You a data from the CCD as soon as I finish that small protoboard.
(Currently - CCD board is finished, FPGA - not, uC - almost completed, test board - not yet.)
I would like to use it as a CCD detector for my spectrograoph, what is Your Idea?
Do You have a method of obtaining TCD ?
Currently I din't find it at any distributor that our reselers work with (schukat, farnell, digikey...).
I have only one peace and I am afraid not to destroy or degradate it.
If You would like to have some contact concernig this subject, contact me at:
nsakan AT phy DOT bg DOT ac DOT yu
(I read it seeral times per day)
If our spam detectio rejects You contact me at the
nsakan AT mail DOT ru
(I read it from time to time)
or here
(same as mail.ru)
Sincerely ,
Nenad
Added after 14 minutes:
I forgot about the ADC - analog devices has done extremley nice IC, 16 bit 15MSPS. It has integrated preamplifier with adjustable offset and gain.
Concerning the AD conversion time, the one cell readout last 4 master clock cycles (4 x 2MHz) on TCD. I need to ssample some data on osciloscope, and the I will have some idea about the form of the signal and the mode of the ADC (I SUPPOSE that I need to use the CDS mode, but...).
The secure time for ADC start would be somewhere on third clock time I think. If You would like to be in touch, I could send You the form of analog signal as soon as I finish the test board.
Sincerely,
Nenad