Interesting question about PMOS bias

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surianova

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pmos bias

Hi all,

I have interesting question here. I want to form a voltage divider (attached) from two same size pmos with power suppy 1.8v. But the question is i connect the gate of the pmos to the source and we know that with this configuration, the pmos is off and will form a high impedence path. In this kind of configuration, can i get 0.9v from the output? Is the voltage divider still working ?

Surianova
 

Re: pmos bias

hmmm..interesting... in this connection pmos are OFF, hence high impedence (very little current flow). In simulation you will still get 1/2 * 1.8 =0.9v output voltage...but i may concern bout the current issue here...

maybe someone else can explain bout this configuration...


regards,
smart
 

Re: pmos bias

the equivalent circuit is two reversed diode connect in series.
like "floating configuration".
from noise consideration, this is a bad reference, cause any noise inject from VSS or VCC will only reduce by 3dB. And if there are noise couple to the center node, it will almost stay there (no reduction is made) and ur 0.9V will be corrupted , and the final value is unknown.
 

pmos bias

some people connect the input and output of the inverter together to divide the voltage.
 

Re: pmos bias


In a digital ic,we know the three states output, I think the circuit like that. so it output a Z states( unstable).
 

Re: pmos bias

Actually, this is not a voltage divider circuit.

You need to tie Gate to Drain to achieve active resistor. This is where your Vgs = Vds, thus the transistor alwiz in saturation mode.

I think you need to understand what is active resistor and how it works.

Hope it helps
 

Re: pmos bias

The topology indeed a bad choice in realizing a stable voltage division option, more to the noise consideration aspect the performance is highly degraded.

Rgds
 

Re: pmos bias

If the PMOS is ideal, the circuit won't act as a voltage divider. It would be similar to having two insulators forming the divider. Even if a small sub-threshold current does flow, I don't think the resistance of both the channels will be the same, and hence the divison will not be perfect. This ofcourse, is in addition to the noise sensitivity.
 

Re: pmos bias

Hey guys forget equations and let's see the real physiscs.

Actually, both transistors will conduct a leakage current. The leakage current will be limited for the less leaky transistor. So the leass leaky transistor will dominate the divider: that is, if the less leaky MOS is above, the output voltage will be near Vdd.
 

pmos bias

Can anybody give an explicitly explanation about why this circuit is sensible to the noise?

Added after 27 seconds:

Can anybody give an explicitly explanation about why this circuit is sensible to the noise?
 

Re: pmos bias

a simple model will self-explained this
1. u could view the two mos are equivalent to two high resistance connect in series.
2. assume them are Rup and Rdown
3. consider a noise source Vn with a series restance Rs ( this is the model of the wire from other nodes to Vref)
4. the transfer function is H=Vref/Vs=(Rup||Rdown)/(Rs+(Rup||Rdwon)),
5. since (Rup||Rdwon) >> Rs , H~=1
6. what's the meaning of H=1 ??? it say Vref=Vs, so the Vref has no immunity to noise, and it is noise sensitive.
 

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