Interconnection of two different layout views.

[santom]

HI all,
I am new to this analog layout designing.I have got two questions to ask you all people.

1. If I have three inverters say A and B and also again A which are of different dimensions(A and B), then I have created the layout of those inverters individually and even did the LVS of it to check its operation.Now when I am trying to connect the two blocks A,B and A, should I just import the layout view of the three inverters in a new layout window and try to connect it.


2.I tried the first step.But I am getting some 'Info hot n-well' error.I just want to know whether there is anything available like ''symbol view for a schematic" for a layout.Will I get a template shape of the single inverter from the layout view of it.


Valuable suggestions and help would be much better and appreciable.

Santom

 

[Pat_Mustard]

Santom

1/ If I am understanding this correctly this sounds like the right methodology. You should create the inverters to be the same height (in the Y-axis) and different widths (in the x-axis), and get them DRC and LVS clean standalone. One all the inverters are finished they can be used as 'sub blocks' within a larger cell.

2/ The error you are experiencing sounds like a substrate problem, have you definately connected the 'Nwell' that the PMOS devices sit in to VDD? Check the substrate connections in the layout. I hope this is of some use, I have never came across a symbol view for layout and dont imagine you need one.

 

[santom]

Hi,
Thanks for the quick reply.Also happy that i made you understand my issue correctly

My substrate connection for both the PMOS and NMOS are connected correctly and it can be confirmed by my LVS match result for the individual inverters.I wouldnt have got the correct result if it has some wrong connections

I am having a huge block diagram.I did the layout of all the small blocks and did the LVS separately.Now I started to merge it one by one and I am getting this error.

For your reference, I will attach the picture of the merged layout of only two inverters with this post.In the picture the left side represents inverter A and the right side inverter B. I just connected both with the metal 1.


Thanks for assisting me.

Santom

 

[Pat_Mustard]

From looking at the diagram I would say that vdd! and gnd! for inverters A and B should be connected in metal also, this could be confusing LVS.

This may well be a warning rather than an error, the fact that it is coming up with the 'info' marker suggests this. Perhaps the compare rules your LVS tool uses does not recognise vdd! as a supply name and so is just warning that the nwell is connected to something other than (what it thinks is) a supply.

 

[santom]

Thanks for the reply and also for the tip.I joined two Vdds and two gnds.

But it is still showing the error as 'Info:Hot nwell'.I am getting kind of confused as where it is going wrong.What could else be an issue in this.

Santom

 

[Pat_Mustard]

I would suggest that it is a warning rather than an error. You will often get warnings whilst doing DRC/LVS verification and it is the engineers responsibility to learn which can be ignored and which are worth investigating further. Look in your design manual for this warning and see what it says, speak to the vendor of your verification tools about the issue too. Whatever you do dont tape out without understanding what the warning is referring too, especially when it involves the substrate.

 

[santom]

OK thanks for the very valuable guidelines you provided me.I will do that.So I think for the moment I will continue connecting all the remaning blocks of my entire schematic's layout to get the whole picture by ignoring the warnings it was giving regarding hot nwel.

But I would like to know the meaning of one more error(related to floating gate) which it is showing for this diagram referred above.

The picture is attached below:



Santom

Added after 28 minutes:

Hi friend,
I resolved that error(related to floating gate) which I asked you in the previous post.

I again defined the pins IN and OUT separately at the merged layout of the two inverters and erased the pins already presented in the individual inverters.

Thanks again for your help.

Santom

 

[Pat_Mustard]

It is to do with your hierarchy, at this level the gate fingers of your PMOS and NMOS connect to metal and nothing else. However once this block is placed in a larger block 'IN' will be driven by something, ie pads, FET, resistor, etc, and this warning will disappear. It is often a good idea to put an antenna diode on the input (gate net) of logic cells as they are typically driven by long thin wires, and so the diode should cut down on Electrical rule check (ERC) errors.