davyzhu
Advanced Member level 1
Hello all,
I encounter a problem when I use a CMOS model (0.6um, China model) to simulate. My workmate use it to simulate asynchronous circuit. And I found the the calculation equation of the rise time do not include gate-source (or gate-drain) capacitor. I guess the Inter-connection (i.e. between two mos stage ) capacitor outweight gate-source (or gate-drain) capacitor, therefore the Cgs is neglected.
I remember the Cgs is about less than 1pF and how about the normal inter-connection capacitor in 0.6um?
The same question about the two capacitors in 0.18um and 0.13um?
Regards,
Davy Zhu
I encounter a problem when I use a CMOS model (0.6um, China model) to simulate. My workmate use it to simulate asynchronous circuit. And I found the the calculation equation of the rise time do not include gate-source (or gate-drain) capacitor. I guess the Inter-connection (i.e. between two mos stage ) capacitor outweight gate-source (or gate-drain) capacitor, therefore the Cgs is neglected.
I remember the Cgs is about less than 1pF and how about the normal inter-connection capacitor in 0.6um?
The same question about the two capacitors in 0.18um and 0.13um?
Regards,
Davy Zhu