I am new to analog design and I have a few questions. I have designed a fully differential folded cascode amplifier, the gain is 70db, bandwidth of 32MHz and a phase margin of 77 degrees. Now I am attempting to create an integrator with this amplifier. I am sampling at 3MHz, and using a switched capacitor network. The problem is that when I calculate what the output of the transfer function is for the integrator I get a gain of 7. When I simulate the circuit I get a gain of 100. I know that I can manipulate the capacitor values to reduce my gain, but I would like to know if there is some other problem with the circuit possibly the amplifier which would cause this discrpancy. The transfer function I am using accounts for finite amplifier gain, and finite bandwidth. Any help would be greatly appreciated.